Assuming we have an analog differential signal trace that we must route from the connector to,say, an ADC (24 bit or 32 bit kind as I don't think lower resolution ones are affected by this.) What we would like to happen is to preserve the signal as much as possible so that our ADC can read as accurately as possible.

I have read that in order for traces to be least likely to be affected by external interference it is best to surround the traces by ground planes above, below and beside. In order to execute this on a PCB (lets not factor external shielding) we must have a lot of vias.

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From what I know, adding vias adds capacitance which we might not want especially at high frequencies. At what frequency do you think 4-6 vias will start being a problem? Is 50kHz still in the clear? How about 1MHz or 100MHz?

At what point do you think that the added EMI protection is not worth it due to signal being affected too much by the vias and the traces should be all be brought back up to the top layer?

  • \$\begingroup\$ You have a connector bringing in your signal and, that will be the likely weak spot so anything you do on the PCB is probably missing the main (problematic) event. Have you looked into 24 bit ADCs to establish how inaccurate the lower few bits are (below 18 bits in reality). A 32 bit ADC will be plain silly. \$\endgroup\$
    – Andy aka
    Commented Dec 8, 2020 at 19:01
  • \$\begingroup\$ @Andyaka Setting aside how accurate the ADC are since there are many more factors that affect their effective number of bits. what would be the better setup purely on a point to point standpoint? I just used the ADC as an example, im pretty sure there are other IC that can benefit better i think. \$\endgroup\$
    – DrakeJest
    Commented Dec 8, 2020 at 19:25

1 Answer 1


A good design will attempt to place the signals on the top layer thus minimizing paraisitc resistance inductance and capacitance, especially if it's a high speed SAR ADC like the LTC2508 or variants of the same core.


Because each of the vias add 5 to 10nH of inductance, which can be a big problem for high frequency signals in the 10's MHz range.

Secondly, if you are running and ADC in the +50MHz range then odds are the ADC will have a matched input and the design will need a transmission line with a controlled impedance. Creating transmission lines that continually switch layers creates problems with matching, keeping them on the top layer eliminates the need for calculating matching with vias and makes the overall design simpler.

The last thing is switching layers also adds the opportunity for cross talk for adjacent signals (so don't run signals across planes or other traces unless you want a few pF's or more of cross capacitance between traces).

If the idea is to shield the signal, then do it with an RF shield over the ADC and the trace.

Look at the EVAL board for the ADC, almost all of them have the traces on the top layer and they are a matched transmission line.

  • \$\begingroup\$ So i see its better to just straight up shield the whole circuit than to mess with switching layers \$\endgroup\$
    – DrakeJest
    Commented Dec 8, 2020 at 19:43
  • \$\begingroup\$ @DrakeJest Switching layers can cause the return currents to also switch layers which creates noise. \$\endgroup\$
    – Aaron
    Commented Dec 8, 2020 at 19:47
  • \$\begingroup\$ You can switch layers, if done right it turns into a complicated mess with having to deal with a lot of calculations with parasitics values from traces and vias (or at least having to worry about them) take the worry away and route everything on the top layer. \$\endgroup\$
    – Voltage Spike
    Commented Dec 8, 2020 at 20:07

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