1
\$\begingroup\$

The data sheet for the CD4013 specifies a "setup time" value, but when you look at the included waveforms, that value describes the timing between the "data" input and the leading clock edge.

What specification do I use to determine the minimum time from a SET or RESET falling edge til the leading clock edge?

There must be enough "daylight" between the falling edge of the SET or RESET input and the clock's rising edge so that these two inputs won't override the clocks ability to "latch" the data on the input.

I like to know how much time is needed between the deactivation of SET or RESET and the first active clock edge to safely latch the data. The t(SETUP) in the data sheet is only shown in the waveforms as the time between the center of the leading edge of the DATA input (either rising or falling) and the center of the rising edge of the clock. At a 5MHz clock (100nSec high, 100nSec low), I need to ensure that the reset signal has "completely" disappeared before the clock leading edge arrives.

\$\endgroup\$
2
  • \$\begingroup\$ What exactly are you asking? Do you want to know how much time you need between the deactivation of SET or RESET and the first active clock edge to safely latch the data? \$\endgroup\$ Commented Dec 10, 2020 at 12:10
  • \$\begingroup\$ Yes, that is exactly correct. The t(SETUP) in the data sheet is only shown in the waveforms as the time between the center of the leading edge of the DATA input (either rising or falling) and the center of the rising edge of the clock. At a 5MHz clock (100nSec high, 100nSec low), I need to ensure that the reset signal has "completely" disappeared before the clock leading edge arrives. \$\endgroup\$ Commented Dec 10, 2020 at 14:44

4 Answers 4

1
\$\begingroup\$

The set and reset are asynchronous. They are not affected by the clock, so they do not have a setup time spec. Most 4013 datasheets have some kind of internal logic diagram.

In a master-slave flipflop commonly used in a D latch, the rising edge of the clock input disables changes in the master ff and enables the slave ff to latch the output state of the master ff. The Set and Reset inputs go directly to the slave ff as extra inputs, bypassing the master-slave relationship and its dependence on a setup time.

\$\endgroup\$
1
  • \$\begingroup\$ In order for asynchronous SET and RESET to work they must control the state of both the master and the slave. These signals do have a setup time requirement...they can't change right at the clock edge and give predictable behavior. \$\endgroup\$ Commented Dec 10, 2020 at 23:34
1
\$\begingroup\$

If you will look at the Fairchild data sheet of the 4013 (Google "108666_DS.pdf" ), you will see that they have not only included the logic diagram of the master-slave connection, but also they have included the interconnection lines between the MOSFET profiles on the die. The master and slave sections of the 4013 are created by cross- coupled "NOR" gates (which can be traced out on the MOSFET interconnect version). You can actually see 4 "NOR" gate MOSFET structures counting from left to right in the diagram. There are also 4 back-to-back-coupled P & N channel MOSFET structures which act as transmission gates: #1 connects one input of the 1st NOR gate to the "D" input. It is "NC" (normally closed) when the clock input is low. #2 connects the output of the second NOR gate back around to the same input on the 1st NOR gate. It is "NO" (normally open) when the clock is low. #3 connects the output of the 1st NOR gate to one input of the 3rd NOR gate. (This is the 1st slave NOR gate). It is "NO" when the clock is low. #4 connects the output of the 4th NOR gate back around to the same slave input on the 3rd NOR gate. It is "NC" when the clock is low.

One spare input on NOR gates #1 & #4 goes to the "SET" input. One spare input on NOR gates #2 & #3 goes to the "RESET" input. So both the "SET" and "RESET" inputs affect both the master AND the slave!

Because the logic structures are negated "OR" structures, if one input is high, the output must be low: the other input is irrelevant. In other words, if either the "SET" input or the "RESET" input is still high when the clock rising edge comes along, the data at the "D" input is ignored.

\$\endgroup\$
1
  • \$\begingroup\$ I don't think you came close to answering the OP's question. What happens if D is 0 and the SET input is deasserted at the same time the clock goes high? \$\endgroup\$ Commented Dec 10, 2020 at 23:37
0
\$\begingroup\$

The SET and RESET are asynchronous to the clock. So long the minimum pulse time is met, it doesn’t matter when they negate with respect to the clock.

\$\endgroup\$
1
  • \$\begingroup\$ Sure it matters. If the state of D is opposite to the condition caused by the SET/RESET, then the SET/RESET cannot change at the same time the clock rises if you expect predictable behavior. \$\endgroup\$ Commented Dec 10, 2020 at 23:38
0
\$\begingroup\$

The SET and RESET do indeed have a setup time requirement. The setup time specification for the D input requires that both SET and RESET be deasserted when that setup time begins, so there is an implied setup time requirement for SET and RESET that is the same as the D setup time.

To illustrate why there must be these timing requirements on SET and RESET, imagine that the SET input is asserted and D is zero. If the SET input is deasserted 1ps before the rising clock edge, what will happen? If you look at the internal structure of the flip-flop, the SET and RESET inputs override the internal feedback path. Any D input change must propagate through this path before the clock changes, so clearly the SET and RESET must be deasserted at the same time, or before, the D input begins its setup time requirement.

EDIT: A relatively modern datasheet from Nexperia refers to this as "recovery time" and provides maximum values.

\$\endgroup\$
2
  • \$\begingroup\$ Thank you very, very much. That information is exactly and specifically what I was looking for. Since I am retired and electronic pursuits must be relegated to hobby status, I am no longer able to keep track of who is manufacturing what and what info their technical documents offer. I am always grateful when I find a forum where a technically qualified person is willing to share precise information. Again, thank you so much for the Nexperia data sheet. \$\endgroup\$ Commented Dec 15, 2020 at 3:00
  • \$\begingroup\$ @machine-code-man Glad I could help. On this site, the preferred practice is for you to "accept" an answer that solved a problem. Accepted answers are always on top, and people who submit good answers get better reputations. \$\endgroup\$ Commented Dec 15, 2020 at 13:19

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.