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I know the channel width can't be smaller, but what about drain and source? Say, in 0.18u technology, what would be a typical drain/source length?

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Be careful...I think you may be mixing up the "width" and "length" terms. Usually, the "length" of the transistor is the smaller dimension and is the dimension we are referring to when we talk about a "180nm process".

The long dimension of the source and drain will be the same as the long dimension (the width) of the transistor's gate, by definition.

The shorter dimension of the source and drain will be determined by design rules that are somewhat independent of the rules for the gate layer, but they will be on the same order of magnitude. However, the minimum size of a source or drain will typically be larger if there are contacts to the silicon. If the source/drain region is shared between two transistors in series then it may not have contacts and may be relatively thinner.

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  • \$\begingroup\$ OK. So, it's process dependent. But what would be a typical value in the examples you gave? \$\endgroup\$
    – MNaz
    Dec 10, 2020 at 19:38
  • \$\begingroup\$ As I said, they will be on the same order of magnitude as the gate minimum length. So perhaps 150nm to 250nm for a 180nm process. The actual numbers are proprietary and protected by NDA. \$\endgroup\$ Dec 10, 2020 at 21:05
  • \$\begingroup\$ I'll also mention that I've seen several processes with a minimum-sized L and a W/L <1, but often times this didn't result in a smaller footprint than the normal "minimum width" device where W/L was between 1-2. \$\endgroup\$
    – W5VO
    Dec 10, 2020 at 21:20
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    \$\begingroup\$ @W5VO I agree. It seems that the minimum implant overlap a contact is usually bigger than the strictly minimum channel width, so you end up moving the contacts farther away from the gate and the whole thing just bigger. \$\endgroup\$ Dec 10, 2020 at 21:56
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These rules are determined by the process used to manufacture these devices. You are right that 0.18u is the minimum for gate length and other features might obey different constraints. For example metal-to-metal minimum distance on the same layer might be down to 0.1u. Typically these will be of a similar order of magnitude, but you'd need to inspect a particular technology to know the exact numbers. When designing a chip your layout undergoes a series of checks known as "Design Rules Check" (DRC) that proof it against those constraints.

As to the minimal width of drain and source this is rarely a process constraint, but rather a design one. You don't want to have very thin wires, since that increases drain and source resistance leading to increased switching times. You can look up standard cell layouts in literature and visually gauge how gate length compares to source and drain sizes in professional designs.

Also, I'm not sure about those cutting-edge 7nm FinFET technologies, maybe they do some fancy 3D design, but in the end I suspect they are running into the same problems.

In short: technically yes, practically no.

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