I have initialized a single port BRAM (clk,din,dout,addr,we) 8X10 with .coe file. I want to read from BRAM and write into the 2D array of dimension 10X8. As the dout of BRAM is 8 bit but the width of array is 10 basically, I want to do transpose. Kindly suggest me some solution. Please zoom the image below for better details.
entity dummy_handle is
Port ( clk : in STD_LOGIC;
--test : out STD_LOGIC_VECTOR(7 DOWNTO 0);
rst : in STD_LOGIC);
end dummy_handle;
architecture Behavioral of dummy_handle is
type array2D is array (0 to 7,0 to 9) of STD_LOGIC;
signal M: array2D;
signal addr_array : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
signal we_A: STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
signal addr : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
signal din : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal test : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal i : integer:= 0;
signal j : integer:= 0;
COMPONENT array_print
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
begin
test <= dout;
print_array : array_print
PORT MAP (
clka => clk,
wea => we_A,
addra => addr,
dina => din,
douta => dout
);
dat_process: process(clk,addr,i,j,test)
begin
if rising_edge(clk) then
if j = 9 and addr = "1001" then
addr <= "0000";
j <= 0;
i <= 0;
else
M(to_integer(unsigned(addr_array)),j) <= test(i);
addr_array <= addr_array + 1;
i <= i + 1;
if addr_array = "111" then
j <= j + 1;
addr <= addr + 1;
addr_array <= "000";
end if;
end if;
end if;
end process dat_process;
end Behavioral;
This is my code,it works ok for 0th column of array , but rest of the column upto 9 is showing undefined. It is not updating j.
This is the test bench.
ENTITY dummy_handle_test IS
END dummy_handle_test;
ARCHITECTURE behavior OF dummy_handle_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dummy_handle
PORT(
clk : IN std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dummy_handle PORT MAP (
clk => clk,
rst => rst
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
dout is the out of BRAM, and it is of 8 bit ,how can we make it as a 10 bit and also I am not able to understand the long and short vector point, it will corrupt the original data ,i think.Pls help me in that.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;