I have a problem with a simple comparator circuit. The comparator takes a 1 PPS (pulse-per-second) signal as a single-ended input, and outputs an LVDS signal.
The issue is that the comparator, ADCMP604, consistently re-triggers on my input pulse's falling edge for some unknown reason, so I end up with a glitch directly following the main pulse width.
LVDS OUTPUT (using Keysight N2751A probe)
The PPS is input on an SMA port from a SpectraDynamics pulse distribution amp (which itself takes a pulse from a Rubidium clock for distribution.)
The LVDS output (STOP_0D_P/N) terminates with a 100 Ω resistor just before its receiver. I have tried everything I can think of:
- Removed the ferrite bead
- Replaced R301 with 33.2 Ω and added 16.9 Ω (2x 8.45 Ω) in series with PPS_IN
- Added additional parallel caps to C68
- Scaled the R294, R302 voltage divider down - here I left the divider output (ratio) @ 1 V, but scaled the resistors in case I was running into input bias current issues
- Changed the 100 Ω termination to 50 Ω + 50 Ω with a cap to ground in-between
- Replaced C72 with 1 μF
- Increased the trigger level from 1 V to 1.6 V (or so)
- A few other things that are slipping my mind
Nothing worked - though increasing the trigger level helped (the glitch reduced, though wasn't eliminated).
If I use the raw Rubidium (Rb) clock output as PPS_IN (as opposed to the output from the distribution amp) it works fine. The Rb output has a much slower rise time and does not undershoot on the falling edge.
So, I suspect it relates to either the freq. content or the undershoot.
This is a view of the falling edge of the input PPS (note the undershoot):
And this is a conglomerate view of the input pulse, trigger level, and LVDS output:
Notes on above:
- The input signal is shown in cyan(?)
- The trigger level (R294, R302 voltage divider) is shown in brown
- The scales of the cyan and brown are the same (as shown at the top of the image)
- This is important to note, since the input signal's undershoot never re-crosses the trigger (and hence, in theory, the glitch shouldn't exist)
- The LVDS output is shown in yellow, measured using a diff probe, range +/- 400 mV
This is driving me crazy. Any suggestions are welcome.
Below is a view of the layout. I highlighted the relevant path in green. For scale, most components (including R56) are 0603.
R265 leading in from the SMA port is 0 Ω.
R55 and R58 on the diff pair traces are also 0 Ω.
R56 is the 100 Ω termination resistor.