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I have a problem with a simple comparator circuit. The comparator takes a 1 PPS (pulse-per-second) signal as a single-ended input, and outputs an LVDS signal.

The issue is that the comparator, ADCMP604, consistently re-triggers on my input pulse's falling edge for some unknown reason, so I end up with a glitch directly following the main pulse width.

LVDS OUTPUT (using Keysight N2751A probe) LVDS output

SCHEMATIC schematic

The PPS is input on an SMA port from a SpectraDynamics pulse distribution amp (which itself takes a pulse from a Rubidium clock for distribution.)

The LVDS output (STOP_0D_P/N) terminates with a 100 Ω resistor just before its receiver. I have tried everything I can think of:

  • Removed the ferrite bead
  • Replaced R301 with 33.2 Ω and added 16.9 Ω (2x 8.45 Ω) in series with PPS_IN
  • Added additional parallel caps to C68
  • Scaled the R294, R302 voltage divider down - here I left the divider output (ratio) @ 1 V, but scaled the resistors in case I was running into input bias current issues
  • Changed the 100 Ω termination to 50 Ω + 50 Ω with a cap to ground in-between
  • Replaced C72 with 1 μF
  • Increased the trigger level from 1 V to 1.6 V (or so)
  • A few other things that are slipping my mind

Nothing worked - though increasing the trigger level helped (the glitch reduced, though wasn't eliminated).

If I use the raw Rubidium (Rb) clock output as PPS_IN (as opposed to the output from the distribution amp) it works fine. The Rb output has a much slower rise time and does not undershoot on the falling edge.

So, I suspect it relates to either the freq. content or the undershoot.

This is a view of the falling edge of the input PPS (note the undershoot): input PPS

And this is a conglomerate view of the input pulse, trigger level, and LVDS output:

conglomerate view

Notes on above:

  • The input signal is shown in cyan(?)
  • The trigger level (R294, R302 voltage divider) is shown in brown
  • The scales of the cyan and brown are the same (as shown at the top of the image)
    • This is important to note, since the input signal's undershoot never re-crosses the trigger (and hence, in theory, the glitch shouldn't exist)
  • The LVDS output is shown in yellow, measured using a diff probe, range +/- 400 mV

This is driving me crazy. Any suggestions are welcome.

Appendix:
Below is a view of the layout. I highlighted the relevant path in green. For scale, most components (including R56) are 0603.

R265 leading in from the SMA port is 0 Ω.

R55 and R58 on the diff pair traces are also 0 Ω.

R56 is the 100 Ω termination resistor.

PCB View

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  • \$\begingroup\$ Is adding more hysteresis to the comparator an option in your judgment of your design and the requirements? \$\endgroup\$
    – nanofarad
    Dec 11 '20 at 5:02
  • \$\begingroup\$ @nanofarad Thanks for the reply. It don't think it would help given the fact that the circuit works fine when provided an input pulse with a significantly slower rise time. \$\endgroup\$ Dec 11 '20 at 5:04
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For decoupling the power supply to the comparators, the data sheet says use multiple 10 nF decoupling capacitors and not a 100 nF capacitor. There is a reason.

enter image description here

You should read the data sheet and understand why 10 nF is preferred over 100 nF in high speed applications.

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  • \$\begingroup\$ Wow, I hope this is right. I’ll try it as soon as I can. Thanks! \$\endgroup\$ Dec 11 '20 at 10:38
  • \$\begingroup\$ Just a quick update: I tried replacing the 0.1 with 0.01 and saw no change (improvement or otherwise). I only have the one pad, but after the holiday I’ll get one our experts to stack (vertically or side-by-side) a few. My hands aren’t steady enough for that kind of thing. I’m thinking it might not help though, considering the unchanged results so far. \$\endgroup\$ Dec 22 '20 at 1:04
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Some things to check.

Signal integrity on Vn (shown, looks OK).

Ditto on VCC : as Andy points out, the right decoupling is crucial (and this is a likely candidate)

Change the shape of the overshoot on the input. (For example, add a 75 ohm series termination at its source). Does that affect the output much?

Look at both Q and Qn (only Q-Qn shown) ... treat these as transmission lines ... is anything bouncing back from an impedance mismatch at the far end? On the LVDS output, where are you looking? at the output or at the receiver? any differences between these points? what does each leg look like on its own?

Note also one point in the datasheet (p.11, top):

The ADCMP604/ADCMP605 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI − 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal is driven past the switching threshold).

this hints at some variation in performance with excessive input overdrive : it may be worth attenuating the Vp input to say 1Vp-p (centred around Vn) to see if this is related to a combination of that ground bounce and excess overdrive.

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  • \$\begingroup\$ Thanks for the suggestions. In addition to my 2nd bullet about splitting the 50 Ohm input, I did also try adding 8.45 in series (replacing R265) while leaving the 49.9 Ohm in place. That had no effect. I’ll try something closer to your suggestion. \$\endgroup\$ Dec 11 '20 at 15:08
  • \$\begingroup\$ Typically I am looking across the 100 Ohm R56. I also probe between R55 and R58 (both 0 Ohm, which I forgot to mention). I have also checked directly across pins 1 & 4 (Q - Qn). They all look very similar. \$\endgroup\$ Dec 11 '20 at 15:11
  • \$\begingroup\$ those R's ... don't seem to be on the schematic. \$\endgroup\$ Dec 11 '20 at 15:15
  • \$\begingroup\$ Yeah, sorry. They’re shown in the layout. I didn’t include them in the schematic because they are off-sheet. Even though the traces are physically short, all of the SMA inputs are logically grouped on one sheet, separate from the receiver. \$\endgroup\$ Dec 11 '20 at 15:22
  • \$\begingroup\$ OK I still think it's worth looking at each leg on its own, gnd plane to R55, ditto to R58. And worth mentioning make/model of probe. \$\endgroup\$ Dec 11 '20 at 15:27

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