I have a 9 X 8 memory with me, there are 9 memory addresses with a byte of data in each.
I need to transfer the contents of this memory to a sub module but I'm one cycle.
module top (input rst, input clk) reg [7:0]mem1[0:8]; wire data_out; smallmem sm (.clk(clk), .data_in(data_out)); endmodule module smallmem (input clk,input [7:0] data_in ) reg [7:O] mem2 [0:9]; . . endmodule
I need to transfer the whole data of mem1 of my top module to mem2 of my submodule smallmem.
Also, can the memory be written this way?
Consider the following snippet
module(input clk, input rst); reg [7:0] buff [0:8]; reg [215:0] mem [0:254]; // Assuming I have a memory 'mem' with the dimensions as stated above // and assuming the value of reg addR at the current posedge of clk is //0. always@(posedge clk) begin for(n=0;n<9;n=n+1) begin mem[(addR+0)][215-(24*n):208-(24*n)] <= buff[n][7:0]; mem[(addR+1)][215-(24*n):208-(24*n)] <= buff[n][7:0]; mem[(addR+2)][215-(24*n):208-(24*n)] <= buff[n][7:0]; end end
Assuming the value of addR is 0. If I run this design for one clock pulse will all the contents of memory 'buff' be written in the first three address of my memory 'mem'? I want content of addresses 0,3,6 of 'buff' to go in 1st,4th,7th,10th,13th,..,25th byte from MSB of 'mem'. Content of address 1,4,7 of 'buff' to go in 2nd, 5th, 8th, .. ,26th byte from MSB of 'mem' and Content of address 2,5,7 of 'buff' to go in 3rd, 6th, 9th, ... , 27th byte from MSB of 'mem'.