# Tuned common emitter amplifier design

I am trying to learn electronics with the help of the Art of Electronics From Horowitz and Hill. I am working on transistors and amplifiers and I am currently working on problem 2.16: Design a tuned common emitter amplifier stage to operate at 100kHz. Use a bypass emitter resistor and set quiescent current at 1mA. Assume Vcc is 15V, L = 1mH and put a 6.2k resistor across LC to set Q=10. Use capacitive input coupling.

There is already a question asked here about the same problem, but here I would like to have someone check my design process and see if I am doing things in the right way.

So this is what I did:

1. I calculated the value of the capacitor $$\C_2\$$ in the resonant circuit to resonate at 100kHz. That turned out to be $$\frac{1}{2π*f_c*\sqrt{LC}} = 2.53nF$$
2. I set the emitter resistor $$\R_3\$$ to be 1kΩ to give enough feedback; at 1mA emitter current $$\V_E\$$ is set at about 1V and $$\V_B\$$ at about 1.7V;
3. I set the emitter bypass capacitor $$\C_1\$$ to be 3.3μF, which gives me a reactance at 100kHz of about 0.5Ω (I wasn't sure how to set this value differently, so I just aimed for a reactance below 1Ω).
4. Knowing that the impedance looking into the base of the transistor is $$\βR_E\$$, I set my bias resistor network to be $$\0.1βR_E\$$ = 10kΩ (I assumed β=100 and omitted the intrinsic emitter resistance) . For $$\V_B\$$ of 1.7V, the ratio between $$\R_1\$$ and $$\R_2\$$ turned out to be $$\R_2\$$ = 0.128 $$\R_1\$$, and I calculated $$\R_1\$$ to be 88.1kΩ and $$\R_2\$$ to be 11.3kΩ, which gave me the required parallel input resistance looking into the base of 10kΩ
5. I selected $$\C_3\$$, i.e. the input coupling capacitor value calculating the total parallel resistance into the base of the transistor given by $$\frac{1}{R_B}=\frac{1}{R_1}+\frac{1}{R_2}+\frac{1}{βR_E}$$ This turned out to be about 9kΩ. Given that Q=10 gives me a bandwith of the resonant frequency +/-10kHz , I calculated the value of $$\C_3\$$ at 90kHz and -3dB to be approximately 200pF

Below is the circuit. I set the load $$\R_5\$$ to be 100kΩ to not load the transistor output ($$\R_{load} >> R_c\$$).

When I simulate the circuit, it seems to work; however, I get an 18Vpp waveform at 100kHz (0.4Vpp input sinewave at 100kHz). How can that be higher than 15Vcc? The bode plot looks also very ugly... why?

Is my approach to designing a circuit correct? Would this design be OK for the purposes of the exercise?

Many thanks!

• Voltage (p-p) can approach 2xVcc. Consider that the mean Vout is Vcc and the negative peak could approach Ve. So that's good. Bode plot looks as if there aren't enough discrete frequencies (the interpolation between them is ... odd, but with enough frequencies it won't matter). Otherwise looks reasonably OK. I'd also double C3 : unless you had a reason for 3dB loss. Dec 11 '20 at 18:47

## 1 Answer

The bode plot looks also very ugly... why?

The bode plot looks ugly because of you not telling LTSpice to use more frequency events (points) when doing the AC analysis. It'll be smoother when you use loads more points but it'll take longer to draw (a minor issue for this circuit).

I get an 18Vpp waveform at 100kHz (0.4Vpp input sinewave at 100kHz). How can that be higher than 15Vcc?

You can get more voltage out p-p that the DC rail because the inductor acts like a short at DC and therefore Q1's collector naturally sits at +15 volts. When you apply a signal, due to the inductor, the AC collector voltage swings above and below the 15 volt DC power rail hence, the maximum p-p voltage will be nearly twice 15 volts. It is degraded slightly by the emitter voltage (1 volt) so the "real" maximum will be about 28 volts p-p before things start to get ugly in the time domain.