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I have been scratching my head with this one for a while. Probably a simple problem to people familiar with VHDL on Vivado.

I have inserted all my code below. I am creating a 32 bit register from D type FF's with an enabler block to load its stored value out. Basically this circuit where set is the clock in VHDL:

enter image description here

I have tested the register and am happy with its functionality. The enabler was added into the project and now I am getting an error when synthesising. Below is an image of my error message:

enter image description here

It is saying my top_level file and the top_level_tb file have difference somewere but I cannot find my mistake. I think it is something to do with the component instantiations.

Thanks for anyone taking the time to help!

Data_Bus_Size_Package


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

package Architecture_size is
 constant Data_width : integer := 32;
 subtype Data_Size is std_logic_vector(Data_width-1 downto 0);
end package Architecture_size;

Top_Level

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.Architecture_size.ALL;

entity Top_Level is
 Port ( Data_in : in std_logic_vector(Data_width-1 downto 0);
        Reset_in : in std_logic;
        Clock_in : in std_logic;
        Enable_in : in std_logic;
        Data_out : out std_logic_vector(Data_width-1 downto 0)
      );
end Top_Level;
 
architecture Layout of Top_Level is

component D_Type_FF_Register is
 Port ( D : in std_logic_vector(Data_width-1 downto 0);
        Clock : in std_logic;
        Reset : in std_logic;
        Q : out std_logic_vector(Data_width-1 downto 0)
      );
end component;          

component Enabler_Block is
 Port ( A : in std_logic_vector(Data_width-1 downto 0);
        Enable : in std_logic;
        Q : out std_logic_vector(Data_width-1 downto 0)
      );
end component;

signal temp_wires_0 : std_logic_vector(Data_width-1 downto 0);

begin

Register_instance : D_Type_FF_Register port map (D => Data_in , Q => temp_wires_0 , Clock => Clock_in, Reset => Reset_in); 
Enabler_instance : Enabler_Block port map (A => temp_wires_0 , Q => Data_out , Enable => Enable_in);

end Layout;

Top_Level_TB


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.Architecture_size.ALL;
 
entity Top_Level_TB is
end Top_Level_TB;
 
architecture simulation of Top_Level_TB is 
 
component Top_Level is
 Port ( Data_in : in std_logic_vector(Data_width-1 downto 0);
        Reset_in : in std_logic;
        Clock_in : in std_logic;
        Enable_in : in std_logic;
        Data_out : out std_logic_vector(Data_width-1 downto 0));
 end component; 
  
   signal Data_in_TB  : std_logic_vector(Data_width-1 downto 0) := "00000000000000000000000000000000";
   signal Clock_in_TB : std_logic := '0';
   signal Reset_in_TB : std_logic := '0';
   signal Enable_in_TB : std_logic := '0';
   signal Data_out_TB : std_logic_vector(Data_width-1 downto 0);
 
   constant clock_period : time := 10 ns;
 
begin
 
   uut: Top_Level port map (
          Data_in => Data_in_TB,
          Clock_in => Clock_in_TB,
          Reset_in => Reset_in_TB,
          Enable_in => Enable_in_TB,
          Data_out => Data_out_TB);

   clock_process :process
   begin
        Clock_in_TB <= '0';
        wait for clock_period/2;
        Clock_in_TB <= '1';
        wait for clock_period/2;
   end process;
 
   stim_proc: process
   begin        
     
     wait for 100 ns;   

     wait for clock_period*10;
       
     Reset_in_TB <= '0';
     Enable_in_TB <= '0';
     Data_out_TB <= "00000000000000000000000000000000";
     wait for clock_period*2;
     
     Reset_in_TB <= '0';
     Enable_in_TB <= '0';
     Data_out_TB <= "11111111111111111111111111111111";
     wait for clock_period*2;
     
     Reset_in_TB <= '0';
     Enable_in_TB <= '0';
     Data_out_TB <= "00000000000000000000000000000000";
     wait for clock_period*2;
     
     Reset_in_TB <= '0';
     Enable_in_TB <= '0';
     Data_out_TB <= "11111111111111111111111111111111";
     wait for clock_period*2;
     
     Reset_in_TB <= '0';
     Enable_in_TB <= '1';
     Data_out_TB <= "11111111111111111111111111111111";
     wait for clock_period*2;
     
     Reset_in_TB <= '0';
     Enable_in_TB <= '0';
     Data_out_TB <= "11111111111111111111111111111111";
     wait for clock_period*2;
    
   end process;

end;

D_Type_FF_Register


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Architecture_size.ALL;

entity D_Type_FF_Register is 
 Port ( D : in std_logic_vector(Data_width-1 downto 0);
        Clock : in std_logic;
        Reset : in std_logic;
        Q : out std_logic_vector(Data_width-1 downto 0));
 end D_Type_FF_Register; 

architecture Behavioral of D_Type_FF_Register is

component D_Type_FF is
 Port ( D : in std_logic;
        Clock : in std_logic;
        Reset : in std_logic;
        Q : out std_logic);
 end component; 

begin

bits: for i in 0 to Data_width-1 generate
instance: D_Type_FF port map (D => D(i), Q => Q(i), Clock => Clock, Reset => Reset );
end generate;

end Behavioral;

D_Type_FF



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Architecture_size.ALL;

entity D_Type_FF is
 Port ( D : in std_logic;
        Clock : in std_logic;
        Reset : in std_logic;
        Q : out std_logic);
 end D_Type_FF;

architecture Behavioral of D_Type_FF is

begin

  process (Clock, Reset)
  begin
    
    if (Clock'event and Clock='1') then 
        if Reset = '1' then Q <= '0';
        else Q <= D;   
        end if;
    end if;
  end process;

end Behavioral;

Enabler_Block



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Architecture_size.ALL;

entity Enabler_Block is
 Port ( A : in std_logic_vector(Data_width-1 downto 0);
        Enable : in std_logic;
        Q : out std_logic_vector(Data_width-1 downto 0));
end Enabler_Block;

architecture Behavioral of Enabler_Block is

component One_Bit_Enabler is
 Port ( A : in std_logic;
        Enable : in std_logic;
        Q : out std_logic);
 end component;

begin

bits: for i in 0 to Data_width-1 generate
instance: One_Bit_Enabler port map (A => A(i), Q => Q(i), Enable => Enable);
end generate;
 
end Behavioral;

One_Bit_Enabler



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Architecture_size.ALL;

entity One_Bit_Enabler is
 Port ( A : in std_logic;
        Enable : in std_logic;
        Q : out std_logic);
 end One_Bit_Enabler;

architecture Behavioral of One_Bit_Enabler is

begin

 Q <= A and Enable;
 
end Behavioral;

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  • 1
    \$\begingroup\$ Did you compile the package? \$\endgroup\$
    – Mitu Raj
    Dec 12, 2020 at 22:32
  • \$\begingroup\$ @MituRaj Yeah it is in the list of complied source files \$\endgroup\$
    – David777
    Dec 12, 2020 at 22:34
  • 1
    \$\begingroup\$ Looks like tool specific. Disable incremental compilation from advanced settings under simulation and try again. \$\endgroup\$
    – Mitu Raj
    Dec 13, 2020 at 0:20
  • \$\begingroup\$ @MituRaj I disabled incremental compilation and still have the same synthesis errors. \$\endgroup\$
    – David777
    Dec 13, 2020 at 10:08
  • 1
    \$\begingroup\$ Did simulation work? \$\endgroup\$
    – Mitu Raj
    Dec 13, 2020 at 10:23

1 Answer 1

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Everyone, just letting you know I found the mistake. It happened to be in my test bench file. Under the stim proc, where I am stimulating the inputs with various values, I actually try to write to the output instead if the input values!

You can see I try to set data_out_TB equal to "00000000" or "FFFFFFFF", instead of writing to data_in_TB. This is shown in the image below:

Image showing my mistake

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