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I keep finding many I2C devices that specify Normal (100 KHz), Fast Mode (400 KHz) and High Speed (3.4 MHz) operation, but make no mention of Fast Mode Plus (1 MHz).

Would you expect these to support it nonetheless?

Here's one example: MCP4728 although I'm mostly looking for an answer that's not device-specific.

Things I'm wondering:

  • Is the same circuitry typically used for all I2C modes (and therefore intrinsically capable of MHz range operation), or is there usually a separate HS circuit on the device that kicks in when the host sends the HS command?

  • Do some manufacturers just not recognise Fast Mode Plus as a standard?

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    \$\begingroup\$ Would you mention even one device, like make/model or link to datasheet? \$\endgroup\$
    – Justme
    Commented Dec 13, 2020 at 10:55
  • \$\begingroup\$ I'm really hoping for a non-device-specific answer, as qualified or anecdotal as it may be, rather than help with a particular device. \$\endgroup\$ Commented Dec 13, 2020 at 11:26
  • \$\begingroup\$ I'm really hoping to see a specific example if there is a particular reason it would or would not support 1 MHz FM+ mode. \$\endgroup\$
    – Justme
    Commented Dec 13, 2020 at 11:59
  • \$\begingroup\$ I've added some info on the original question. \$\endgroup\$ Commented Dec 13, 2020 at 12:27
  • \$\begingroup\$ The datasheet rules. Don't look for "assumptions" that you can make in the absence of evidence. \$\endgroup\$ Commented Dec 13, 2020 at 13:31

2 Answers 2

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There's nothing to support the assumption that fast mode operation is supported: for example, you need to synthesize a 1 MHz clock for that, and so far your device doesn't say it does that.

In general, and especially here: if some functionality isn't specified in the datasheet, you can't make assumptions on its presence – full stop.

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  • \$\begingroup\$ Isn't it the job of the host/master to synthesize the clock? \$\endgroup\$ Commented Dec 13, 2020 at 14:03
  • \$\begingroup\$ @Damien it is, but that's the general answer. Notice that a slave might not have appropriate clock-stretching logic for any but the recommended rates, especially if it derives internal clocks from the master. \$\endgroup\$ Commented Dec 13, 2020 at 14:05
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There may be a bit of a difference in the internal circuitry to decode the extra "special address byte of 00001XXX following the START bit" as stated in the datasheet. There doesn't seem to be any limitation on the lower frequency so you may be able to use 1 MHz with High speed mode:

MCP4728 5.1.1

MCP4728 I2C Freq

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