As per shown in the below schematic, I have two ADG714(datasheet) octal SPST analog switches connected in the daisy chain configuration.
Enable/CS - Synch
IC8's SCKL, Synch pins are tied with controller and IC7's SCLK and Synch pin respectively. Dout of IC7's is connected to Din of IC8 through 4.7k ohms pull-up resistor because Dout is open drain. SLCK is of 18Mhz. Supply voltage:
Vss : -2.5V
as per datasheet, abosolute operating condition Vdd to Vss is 7V
Configuration of the controller's SPI as follow: Half duplex transmitter, 16bits data frame, CPOL = 0, clock phase is negative edge, MSB first and Enable or CS or Synch is controlled through GPIO pin.
I am not getting correct Dout output which should be 8 bits delayed as per the datasheet. Below image is of Logic Analyser.
Channel0 is SCKL
channel3: Dout of IC7
Could you please tell me where I have made mistakes?
EDIT: is it also possible that Pull up resistor's value is high and because of parasitic capacitance, time constant is high and switch can not 'drive' the output correctly? as per the datasheet, sclk raise time to Dout valid output max time is 20ns