D-Flip-Flop Hold and Setup Timing

I am solving some question to prepare for my exam but got stuck on this one and need your help.

Giving the following circuit:

Where input x gets updated 10ns after clock goes down, I'm also given that clock cycle is 50ns such that half of it the clock is 1 and the rest the clock is 0.

Plus giving the following timing table:

I need to calculate T_cd(XOR).

The Final answer is: We can't determine how the circuit behaves those can't find the requested value.

So from this I understand that T_Hold and T_Setup requirements aren't met, So I made a quick check:

Is T_CD(FF1)+T_CD(Logic)>=T_H(FF2)? (In this case FF1 is also FF2 and Logic is XOR and OR gates) Answer: True

Is T_PD(FF1)+T_PD(Logic)+T_Setup(FF2)<=T_clk? (In this case FF1 is also FF2 and Logic is XOR and OR gates and T_clk is the time for full clock circle which is 50ns) Answer: True

Conclusion: T_Hold and T_Setup requirements aren't met thus we can calculate T_cd(XOR).

I think I am missing few things here especially since in my calculation I never used that value of 10ns...

• When things aren't clear in my head, I draw a timing diagram. – Mattman944 Dec 15 '20 at 2:42
• @Mattman944 I did and that didn't help a lot, actually it proved everything is ok – MrCalc Dec 15 '20 at 8:44

The Final answer is: We can't determine how the circuit behaves ... So from this I understand that T_Hold and T_Setup requirements aren't met

Not necessarily the conclusion you should make. If this circuit's behavior cannot be determined, then it may mean timing violations have happened due to -

• Either hold or setup failed.
• Both setup and hold failed.

Where input x gets updated 10ns after clock goes down,

One way you might want to look into this scenario is -

• Imagine there is another flip-flop-A sitting 'before' to launch data to the flip-flop-B in your circuit, which captures that data.
• This data was launched on the rising edge at flip-flop-A, and is supposed to be captured at flip-flop B at the next rising edge.
• The launched data from flip-flop-A then arrives at the input of OR and XOR gates after 10ns (assuming no wire delays, skews), after the clock goes down. It means effectively it passed thru a propagational delay of $$\T_{pd}(in) = T_{clk}/2+10=35 \text{ ns}\$$, before it reaches the input of OR and XOR gates.

So our "imaginary" circuit for timing analysis now looks like -

I guess $$\T_{pd}\$$ and $$\T_{cd}\$$ refer to Propagation and Contamination delays respectively.

Setup Analysis at flip-flop B

Consider the worst-delay path to B (with all propagation delays). By inspection, it is thru -

input delay at x $$\ \rightarrow\$$ XOR $$\ \rightarrow\$$ OR

Math for satisfying Setup:

$$T_{in}+T_{pd}(XOR)+T_{pd}(OR)+T_{setup}(B)\le T_{clk}$$ $$\implies 35+6+7+4\le 50 \text{ ns}$$ $$\implies \bbox[7px,border:1px solid red]{52\le 50 \text{ ns}} \text{ --- violated! }$$

Hence, from setup analysis itself, we can conclude that this circuit has timing violation and hence its behavior is uncertain. However let's do Hold Analysis as well.

Hold Analysis at flip-flop B

XOR's contamination delay is unknown. Okay, anyway let's consider the best-delay path to B (with all known contamination delays). By inspection, it is thru -

$$\\text{clock-to-Q of B}\$$ $$\ \rightarrow\$$ XOR $$\ \rightarrow\$$ OR

Math for satisfying Hold:

$$T_{cd}(clk\rightarrow Q)+T_{cd}(XOR)+T_{cd}(OR)\ge T_{hold}$$ $$\implies 5+T_{cd}(XOR)+4\ge 10 \text{ ns}$$ $$\implies \bbox[7px,border:1px solid black]{T_{cd}(XOR)\ge 1 \text{ ns}}$$

The above is true if Hold is assumed to be satisfied in the circuit (which is not mentioned in your question, nor we can conclude). If Hold is also assumed to be violated, then $$\T_{cd}(XOR)\$$ should be: $$\implies \bbox[7px,border:1px solid black]{T_{cd}(XOR)< 1 \text{ ns}}$$

• what I don't understand is why in Setup Analysis you didn't consider T_pd of FF? that is what I learnt plus where these 35 came from? – MrCalc Dec 15 '20 at 8:39
• "It means effectively it passed thru a propagational delay of 𝑇𝑝𝑑(𝑖𝑛)=𝑇𝑐𝑙𝑘/2" why 𝑇𝑐𝑙𝑘/2? – MrCalc Dec 15 '20 at 8:42
• In Hold Analysis why didn't you take Tcd(clk -> Q) for the FF that you just added too? – MrCalc Dec 15 '20 at 8:46
• In setup, you have to take the worst delay path. There are three setup paths. I took the worst delay path for analysis. In that path, tpd of B doesn't come into picture. – Mitu Raj Dec 15 '20 at 8:51
• Tclk/2, because the given delay of 10 ns is measured from falling edge (as per the question). So half cycle delay has to be added to find the total delay from rising edge. – Mitu Raj Dec 15 '20 at 8:53