(note: this post has been updated as suggested by members)

The schematic below shows a single coil to be pulsed by n & p FETs. Each FET has 100V ds breakdown and < 10 mOhm Rds. Vgs threshold is +/- 2V for each. Vgs max = +/- 20V. There is no possibility for both FETs to have low Rds at the same time.

coil pulsing in either direction

The objective of the circuit is to pulse a single coil in either direction. Each pulse should be considered independent of those prior - there is no timing relationship between pulses other than a minimum time interval between them. This is not a motor driver. Pulses aren't alternating. The coil is being used to repel a magnet. There will be significant concerns due to the magnet - I have a good understanding of those concerns and am only interested in the circuit provided (i.e. without magnet).

Once I know how to protect the FETs I will push the circuit right to the point where Vds is almost exceeded. I could get FETs of Vds max = 120V but question would be the same with rails at +/- 60V instead of 50V. I could keep going until Rds is too large or FETs get too expensive, so these specific values aren't the point of my post. The idea is to push the limits while protecting the FETs.

The coil shown is ~ 40mH with internal resistance 140 ohms, but I am interested in general principles that work for variable coil parameters. Assume between 5mH and 100mH. Vdd may be as low as 12V and as high as 50V as I experiment with pulse widths, duty cycles and field strengths. I realize back EMF may be significant, and I'm not sure how to protect the FETs other than to just lower Vdd. Current demand per pulse will be way below FET capability.

Consider gate signals to be wired correctly. Assume the circuit is perfect on that side of the schematic - it will not be a challenge. (unfortunately I didn't state this well upon first posting and there was a lot of confusion on that point. many apologies to those that wasted time because of it).

Last point which I'm sure some will ask me regards pulse widths and duty cycle. The hope is to create pulses at widths between 0.1ms and 2ms. Duty cycle flexible depending on noise, heat, ringing and of effects from back EMF. The ideal case which I don't expect to achieve: 0.5ms pulses that aren't a terrible mess (some ringing/noise will be acceptable). Current between 0.15A and 0.5A. Duty cycle 0.3 max. The final result can be a bit off from this and I'll be happy.

Many thanks for everyone's help already, specifically DKNguyen and Bruce Abbott!

  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. \$\endgroup\$ – Voltage Spike Dec 16 '20 at 17:03
  • \$\begingroup\$ Hazy the problems usually stem from inadequate assumptions stated then moving targets like adding 5.1k changes the answer to the "simple" question from Yes to No. Then the question goes from bad to worse due to more missing assumptions. Like is the load an inductor or a motor with inertia, then how much. So it's not worth my time, even though I wasted it in this simulation tinyurl.com/y8tksez3 This a common fault to this site and the Socratic Method ends up being a really long discussion of irrelevant info \$\endgroup\$ – Tony Stewart EE75 Dec 16 '20 at 17:21
  • \$\begingroup\$ All questions MUST include all the design requirements and assumptions or SPECS which are MISSING in the question. Purpose, inputs, outputs. (/w measureable parameters) Keep it simple but complete. \$\endgroup\$ – Tony Stewart EE75 Dec 16 '20 at 17:26
  • \$\begingroup\$ changing load and f changes everything for power but not voltage with ratios , still no idea on purpose tinyurl.com/y9xe4kzn -1 \$\endgroup\$ – Tony Stewart EE75 Dec 16 '20 at 17:35
  • 1
    \$\begingroup\$ and of course there's a downvote again ensuring that I don't improve and come up to speed. don't pay attention to the new guy! we don't like people who enjoy learning! \$\endgroup\$ – hazyj Dec 16 '20 at 18:59

If your goal is to pulse the electromagnet in alternately reversing polarities then you can either use a half-bridge:


simulate this circuit – Schematic created using CircuitLab

Or an H-bridge:


simulate this circuit

You can use clamp diodes, TVS diodes, or RC snubbers or combinations thereof to control the inductive kick.

The vast majority of discrete MOSFETs have a parasitic body diode which can serve the same purpose as the rail-clamp diodes in an H-bridge but, being parasitic, they are usually not optimized for the purpose. External rail-clamp diodes will be better.

Rail clamp diodes cannot be used in the half-bridge configuration.

I repeat: Rail clamp diodes cannot be used in the half-bridge configuration, unless you feel like having the flyback current routed through your power supply.

  • Rail-clamp diodes (D1 to D4) will clamp the voltage to the power supply rails. The diodes will have only low heat since they operate in forward bias but that means the energy stored in the magnetic field of the coil will be dissipated in the coil resistance (or R1 if you have it). Will not control dV/dT.
  • RC snubbers Do not clamp to a fixed voltage. Instead they lower the voltage spike compared to what it would have otherwise been. Slow down dV/dT and are faster than diodes since they are "always on", but less efficient as a result. Use capacitors and resistors rated for pulse loads and with low parasitic inductance. Since it works by reducing dV/dT it will help if high dV/dT is causing MOSFET misbehaviour due to transient currents finding their way through the MOSFET parasitic capacitances whereas diodes will not.
  • TVS diodes (D5-D6) Clamps the voltage across the coil to a fixed value. High power dissipation in the diodes since they operate in reverse breakdown. D1 and D2 here are two back-to-back unidirectional TVS diodes or you can use just one bidirectional TVS diode. Will not control dV/dT

For the H-bridge, you can also place TVS diodes or RC snubbers in parallel with the inductance similar to what was done in the half-bridge.

For the same power supply voltages (i.e. for the same 'V'), both half-bridge and H-bridge can apply the same voltage to the coil in both directions. However, the half-bridge requires only two power transistors but requires two voltage supplies whereas the H-bridge requires four power transistors but only one voltage supply.

  • \$\begingroup\$ Thanks!! You've been extremely helpful. I do want to clarify what I think is the key point of my circuit and use case. And to clarify your meaning of your phrase "alternately reversing polarities". As specified, pulses are not alternating. I think you realize that, but I believe it's an important point to make: the coil will never be able to discharge through the opposite FET. \$\endgroup\$ – hazyj Dec 18 '20 at 1:32
  • \$\begingroup\$ An issue with the H-bridge or the version of it in your image is that the coil is represented as inductance without resistance. i.e. you have diode clamps in parallel with pure inductance when realistically there would need to be resistance in series with the inductance for it to be a coil. \$\endgroup\$ – hazyj Dec 18 '20 at 5:43
  • \$\begingroup\$ @hazyj I had assumed the inductor in your circuit was the actual coil and the resistance was something you added so you could use a higher voltage supply than you otherwise could. \$\endgroup\$ – DKNguyen Dec 18 '20 at 7:08
  • \$\begingroup\$ How can a coil be modeled realistically without including its resistance? I mean, in what cases would your clamp be realistic for L1? \$\endgroup\$ – hazyj Dec 18 '20 at 15:45
  • \$\begingroup\$ I suppose that if there was extremely low resistance relative to reactance it works. \$\endgroup\$ – hazyj Dec 18 '20 at 15:47

I simulated a slightly modified version of your circuit in LTspice. Here is the schematic:-

enter image description here

I don't have models for your FETs so I chose the nearest I could find in LTspice.

D1/C1/D2/C2 simulate typical DC power supply outputs. Less than 1 V of ripple was evident at a coil current of 0.5 A.

Q1 and Q2 act as current generators to level-shift the pulse inputs. This produces a Gate drive voltage of ~5.5 V (across R2 and R4) with supply voltages from 12 V to 50 V. Drive current is ~12 mA, which the ESP32 should be capable of (max. recommended GPIO output is 16 mA).

Zener diodes D3 and D4 protect the Gates against possible over-voltage, and C3 and C4 help to swamp out 'miller' feedback voltage. These components may not be necessary, but I put them in for peace of mind considering the relatively high Gate drive impedance of 470 Ω.

R8 damps ringing in the coil when switched off.

Here is a plot of the coil receiving positive current for 1 ms:-

enter image description here

The switching waveform was clean, R8 providing sufficient damping to produce a single flyback pulse with virtually no ringing. No extra flyback diodes or other damping components appeared to be necessary.

The slow rise time is caused by the coil's L/R time constant. Fall time is quicker because with backemf it has twice as much voltage. Backemf increases at the resonant frequency of the coil and parasitic capacitance in the FETs, taking less than half a cycle to reach the opposite supply rail where the other FET clamps it.

With a supply voltage +-50 V the peak voltage across each FET is slightly over 100 V. A margin of at least 20% is recommended, so you should choose FETs rated for 120 V or higher. With only 0.5 amps maximum coil current the FETs don't need to have very low on-resistance.

  • \$\begingroup\$ Wow - this is awesome Bruce!! I was about to wire a circuit to give a similar plot but with much more complicated logic. My drivers are similar to yours - as I mentioned the schematic for those was rushed. I won't keep belaboring why, but the logic is simple for me and wasn't supposed to be a focus. However, all the effort put in there is extremely well appreciated! \$\endgroup\$ – hazyj Dec 18 '20 at 15:09
  • \$\begingroup\$ FYI, since you seem to be interested and since what I'm doing with this is interesting (IMO of course:-) ... the entire goal for me is to look at that plot and choose the shortest pulse width for my purposes. This isn't exactly on topic because heat dissipation will determine what I can get away with, and that dissipation rate will be completely determined by materials and structure and not in any way common EE practices. I have a handle on that part starting with choosing pulse width and duty cycle. So according to your awesome plot ... \$\endgroup\$ – hazyj Dec 18 '20 at 15:17
  • \$\begingroup\$ For my FETs I can choose +/- 42V rails max. I'll get a slightly longer rise time and lower output current than shown in your plot. I can easily ball park the min pulse width for my purposes here: 95% of peak value achieved in about 0.25-0.30 ms. Decay takes approx 0.1 ms: approx 0.3 - 0.4ms total. Duty cycle chosen by heat dissipation constraints. I will find max duty cycle for my purpose, and if still concern about heat pulses can simply be shut off for a reasonable amount of time. I've done this part before. Nothing difficult here because of appropriate pulse with choice. \$\endgroup\$ – hazyj Dec 18 '20 at 15:30
  • 1
    \$\begingroup\$ Please don't put references to my answer in your question, it's fine as is (apart from not including the important extra info you put in the comments) and changing it could affect the relevance of other answers. Please remember that this site is not a discussion group. People mostly come here to get generic answers to questions like "Are external diodes needed to protect these MOSFETs from back emf?" that may relate to their own problems, and are not so interested in the minutae of your project. \$\endgroup\$ – Bruce Abbott Dec 18 '20 at 17:16
  • 1
    \$\begingroup\$ To quickly discharge the coil you need to raise the flyback voltage. A short circuit will make it discharge slower. Again, your circuit is fine as is, don't change it! \$\endgroup\$ – Bruce Abbott Dec 18 '20 at 17:20

The first thing to do would be to determine the overshoot from the mosfet (best done in a simulation), once you do here is the things you need to worry about:

For a mosfet, two parameters found in the datasheet (Vgs and Vds) can't be exceeded or the device will probably fail.

Vgs is the voltage between the gate and the source, for many mosfets its around 15V or 20V.

Vds is much higher but also can't be exceeded.

For the top fet, it's Vgs that becomes a worry, if the inductor is say 40V and the gate at 0V then the gate could easily get blown out if the Vgs were ±20V. So in that case either select a mosfet that has a large Vgs (some go up to 50V, which would cover your application but may not have the other parameter needed for the design so select carefully) or use diodes to reign in the overshoot from the inductor.

  • \$\begingroup\$ I'm finally settling down and getting to my simulations. Concern about exceeding Vgs max has been one of my 2 or three main concerns leading me to post. Yes - current solution has diodes lessening the overshoot as well as RCs in parallel. I believe I've also addressed the possibility of exceeding Vgs but let's see what the simulation has to say. Thanks!! \$\endgroup\$ – hazyj Dec 16 '20 at 19:08
  • \$\begingroup\$ One thing the moderators can't touch is voting, it wasn't a great question to start with so I can see a problem there. Another problem that I don't like with the question is a lack of a specific question statement. \$\endgroup\$ – Voltage Spike Dec 16 '20 at 19:28
  • \$\begingroup\$ fair enough. i'm moving on and, i assure you, improving as well. \$\endgroup\$ – hazyj Dec 16 '20 at 19:30
  • \$\begingroup\$ No worries it takes a bit to get up to speed \$\endgroup\$ – Voltage Spike Dec 16 '20 at 19:32
  • \$\begingroup\$ Why would Vg ever stray far from +/- Vdd for the respective FETs? My schematic shows they will always be following the sources +/- a very well controlled drop due to the dividers shown. Since I stated Vgs +/- 2V (I meant threshold of course) I don't see why there would be any concern that Vg for top FET would ever dive below Vdd - 10V or for bottom FET above -Vdd + 10V. \$\endgroup\$ – hazyj Dec 16 '20 at 19:38

Typically, the MOSFETs should have body diodes pointed in the right direction for protection. Check out some datasheets from integrated fet H-bridges like this one, it's not the same circuit but similar principle.

TI DRV8833 https://www.ti.com/lit/ds/symlink/drv8833.pdf?ts=1608079490506&ref_url=https%253A%252F%252Fwww.google.com%252F

  • \$\begingroup\$ you know, one of the great reasons for asking question on sites like this is to get feedback from competent people that don't tell you "you've missed the point". answers like yours are refreshing because they get straight to the point: although I'm well aware that MOSFETs have body diodes and clearly will help, I still need someone with experience to confirm that they will be enough for the circuit in question. So now I can proceed to lessen overshoot and I believe I'll start seeing some nice looking pulses soon. Thank You! \$\endgroup\$ – hazyj Dec 16 '20 at 19:47
  • \$\begingroup\$ Unless there is something I'm missing, you are talking about Vds exceeding the mosfet ratings due to back emf from the coil on the floating node between the two mosfets? That node is not floating it is clamped to +/- Vdd from the mosfet body diodes, which are not drawn in the schematic. In reference to the title's question, the external diodes aren't needed because the body diodes in the mosfets are already there. \$\endgroup\$ – Colin Parker Dec 16 '20 at 21:30
  • \$\begingroup\$ Not following Colin, but then I'm probably missing something. Let's take an example. Each FET has Vds = 100V breakdown. Let's say Vdd is 50V for my circuit . When the top FET is conducting and then cutoff, the left side of the coil rises above 50V momentarily due to back EMF. Vd from bottom coil is now at 50V+. Vds max has therefore been exceeded. \$\endgroup\$ – hazyj Dec 17 '20 at 4:07
  • \$\begingroup\$ This shows max Vds exceeded (i.e. Vds > 100V in this case) if diodes are removed. tinyurl.com/yaf2of5h Vds plot is at bottom right. I got my voltage backwards in previous comment, so scope shows top Vds for top FET. \$\endgroup\$ – hazyj Dec 17 '20 at 13:59
  • \$\begingroup\$ Look at this: tinyurl.com/y7vl94tj The voltmeter shows peak above Vds \$\endgroup\$ – hazyj Dec 17 '20 at 14:36

The body diode of the opposite MOSFET is in the correct position to protect each MOSFET.

Body diodes are a bit slow and have normal silicon diode Vf. They can be paralleled with Schottky diodes if speed is required, but with 40mH it probably makes no difference.

The initial current through the body diodes will be the coil current and will die off exponentially with a time constant R/L. Your MOSFETs need to withstand Vcc*2 plus a bit. The “bit” needs to handle the diode Vf and any inductance in the power supply circuit. This assumes your supplies are have good bypassing and are well regulated, and have enough bleed current or can sink current to absorb the power from repeated switching.

If you just switch one MOSFET repeatedly, you have made a boost converter and the opposite rail could increase out of regulation if there is nothing to absorb the energy stored in the inductance each cycle.

There are a number of problems with your gate drive- most likely no MOSFET that works properly with 3V drive can withstand more than 8-20V, and the p-channel driver needs work. Also the switching may be too slow.

But you just asked about the diodes.

  • \$\begingroup\$ Yes, I wasn't worried about the gate driver at all. I just rushed it because a LOT of time was wasted trying to install TINA-TI on my mac. It isn't easy! Anyhow, that's why the question seems so off: time wasted didn't allow much time to post. \$\endgroup\$ – hazyj Dec 18 '20 at 0:53
  • \$\begingroup\$ "Your MOSFETs need to withstand Vcc*2 plus a bit." This is one of the main reasons I posted. I've learned a lot about that "bit" since posting, and it's led me to what you just mentioned: good supply and grounds for sinking current for the large energy stored in the coil. I could design around FETs with larger Vds max, but the question would just come up again with different parameters. Anyhow, I don't like that "bit":-( Time to rid my concerns with it by discharging the coil superfast. Easy enough! Thanks Spehro \$\endgroup\$ – hazyj Dec 18 '20 at 1:17

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.