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I am doing multiple comparisons on variable values in VHDL and it won't synthesize using Design Compiler.

I wrote it in VHDL-2008 and newer, but Design Compiler wont synthesize VHDL-2008 and newer.

It does not like the when statements.

How can I clean this comparison up so it can synthesize ?

process begin
    wait until rising_edge(clock);
    if state(7) = '1' then
      b(0) <= '1' when (a(0) = '1' and a(4) = '1' and a(6) = '1') or (not a(6) = '1' and not a(5) = '1') or (not a(6) = '1' and a(5) = '1' and not a(2) = '1') else '0';
      b(1) <= '1' when (not a(4) = '1' and a(6) = '1') or (not a(5) = '1' and not a(6) = '1') else '0';
      b(2) <= '1' when (not a(0) = '1' and a(4) = '1' and a(6) = '1') or (not a(1) = '1' and not a(4) = '1' and a(6) = '1') or (not a(2) = '1' and a(5) = '1' and not a(6) = '1') or (not a(3) = '1' and not a(5) = '1' and not a(6) = '1') else '0';
    end if;
end process;
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  • \$\begingroup\$ Is this VHDL 2008 or newer? \$\endgroup\$
    – user4574
    Commented Dec 15, 2020 at 4:47
  • \$\begingroup\$ I wrote it in VHDL-2008 and newer, but Design Compiler wont synthesize VHDL-2008 and newer. \$\endgroup\$
    – user4434
    Commented Dec 15, 2020 at 4:50

1 Answer 1

2
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  • change "wait until rising_edge(clock)" into an if statement. Some synthesizers don't support "wait until"

  • The code uses a "when" statement inside of a process. This is only going to be supported in VHDL 2008 or newer. If your synthesizer even supports VHDL 2008, it may not be enabled by default.

  • The code uses a lot of "= '1' " in the logic. This is not necessary.

      x <= '1' when (y = '1' and z = '1') else '0';
    

    Is equivalent to...

      x <= y and z;
    

I would suggest the following...

process(clock) is begin
    if rising_edge(clock) then
        if state(7) = '1' then
            b(0) <= (a(0) and a(4) and a(6)) or (not a(6) and not a(5)) or (not a(6) and a(5) and not a(2));

            b(1) <= (not a(4) and a(6)) or (not a(5) and not a(6));
            
            b(2) <= (not a(0) and a(4) and a(6)) or (not a(1) and not a(4) and a(6)) or (not a(2) and a(5) and not a(6)) or (not a(3) and not a(5) and not a(6));
        end if;
    end if; 
end process;
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  • \$\begingroup\$ It doesnt like the when statement in a process as you said, but it is okay with the "wait until rising_edge(clock)" statements. Thanks. \$\endgroup\$
    – user4434
    Commented Dec 15, 2020 at 5:02
  • \$\begingroup\$ What is the " ' " for in the b(1) line ? b(1) <= '(not a(4) and a(6)) or (not a(5) and not a(6)); \$\endgroup\$
    – user4434
    Commented Dec 15, 2020 at 5:16
  • \$\begingroup\$ It was obviously put in there on purpose to make sure people were thoroughly checking my work... Or just a typo... You decide. I can understand why you might have thought it had a purpose since a single quote is used to access attributes in VHDL. \$\endgroup\$
    – user4574
    Commented Dec 15, 2020 at 5:19

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