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I have a question about reading and writing operations.

Say if i wanted to read or write the column WL0, i would enable the WL0 lines.

For either a read of a write i would drive the bit lines to either Vdd or Vdd/2

What about when i don't want an operation to be performed in any row of WL0?

Consider a 1 stored across the capacitor in WL0 and row 2, if WL0 is enabled the capacitor will discharge through the bit line on row 2. If the bit line is 0 initially it increases in voltage, does the capacitor then decrease in voltage? If so, is it fully discharged?

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The sense amplifier is relevant here. You are correct that asserting the word line will connect the DRAM cell to the sense amp, thus allowing its charge to leak.

However, during a read, the sense amp will amplify the tiny voltage still present (actually a differential voltage for improved retention and noise immunity), and with positive feedback, will drive the DRAM cell with that same value. This refreshes the cell, mitigating the fact that charge leaked during the read.

For a write operation, the sense amp is disabled and the data being written is applied to the cell.

With that said, if you don't want any operation to occur on occur on any columns of WL0? Then don't drive WL0. The charge will slowly leak so you'll need a refresh anyway (either by reading that whole row, or by the refresh controller doing so on your behalf).

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