The MIPI I3C Basic standard describes an I2C-like bus with different timing requirements. In particular, that document describes a measure, tSCO, that describes a target device's clock-in to data-out responsiveness.
The maximum standard tSCO is 12 ns, but normally it is only 8 ns per Table 59. Both seem quite hard to implement in programmable synchronous logic, but I guess it makes sense for the I3C standard data rate of 12.5 MHz where the clock period gets down near 80 ns.
I3C can operate at slower clock speeds. My question is does it make sense that tSCO should scale with the clock speed?