I am creating a basic RISC processing core on a FPGA development board (Nexys A7-100t).
I created a RAM block that will be used to store the instructions that my basic processor will execute to run a simple program. I have attached the file code for my RAM block below. Note it is not complete or been tested / compiled so there will be errors but it is just there to give you an idea of the RAM blocks functionality.
This code in theory generates the logic for accessing / sorting data but it doesn't initialize the RAM memory contents to hold the binary instructions.
My question is how could I initialize the RAM block upon power up or FPGA configuration?
My initial thoughts tells me I have the following options:
Generate the data 'manually' with VHDL code and LUT to write the data bytes to the RAM block. This might be the easiest option as there may only be approx 100 memory locations which are 32 bits wide.
Maybe Xilinx provides functionality to achieve this. I am not sure.
Use an SD card with the on-board SD card reader on the development board. Again unsure if this is viable.
Use an EEPROM to store the instructions and upon power up, write this data to the RAM block. I imagine this is no different than method 1. except for the hassle of reading the EEPROM contents serially while still having to load the data 'manually'. I do like the sound of using an EEPROM though.
I am interested to hear how everyone would do this. This is an academic project so doesn't require high speed, just low complexity and something repeatable.
Thanks for any help everyone!
RAM block VHDL file
LIBRARY ieee; USE ieee.std_logic_1164.ALL; --add other required library files that holds 'Data_width' constant entity RAM_Block Port ( RAM_Address : in std_logic_vector (Data_width-1 downto 0)); Data_in : in std_logic_vector (Data_width-1 downto 0)); Clock : in std_logic; Enable : in std_logic; Data_out : out std_logic_vector (Data_width-1 downto 0)); end RAM_Block; architecture Behavioral of RAM_Block is type memory is array (0 to 100) of std_logic_vector (Data_width-1 downto 0); signal RAM : memory; variable RAM_Address_int integer := 0; signal RAM_output : std_logic_vector (Data_width-1 downto 0); component Enabler_Block is Port ( D : in std_logic_vector(Data_width-1 downto 0); Enable : in std_logic; Q : in std_logic_vector(Data_width-1 downto 0)); end component; begin Enabler_Block_instance port map (D => RAM_output , Enable => Enable , Q => Data_out); RAM_Address_int <= conv_integer(unsigned(RAM_Address)); Process (Clock , Enable) begin if(rising_edge(Clock) and Clock = '1') then RAM(RAM_Address_int) <= Data_in; end if; if(rising_edge(Enable) and Enable = '1') then RAM_output <= RAM(RAM_Address_int); end if; end Process; end Behavioral;