I have a clock with a 50% duty cycle, driving a 3-bit ripple counter.
When Q2 is high, external lines such as address are stable. I want to generate a short read pulse between 50% and 75% of the Q2 signal to latch in data from external RAM / ROM.
Below is what I am using in LogiSim. But if I remember back to my digital electronics days (1980!), I can get a glitch between when the counter (Q2, Q1, and Q0) changes state, which might trigger a spurious RdPulse.
Is there a race hazard (e.g., when the counter changes from 111 to 000)? And if so, how can I avoid it?