How can I avoid a clock glitch?

Question

I have a clock with a 50% duty cycle, driving a 3-bit ripple counter.

When Q2 is high, external lines such as address are stable. I want to generate a short read pulse between 50% and 75% of the Q2 signal to latch in data from external RAM / ROM.

Below is what I am using in LogiSim. But if I remember back to my digital electronics days (1980!), I can get a glitch between when the counter (Q2, Q1, and Q0) changes state, which might trigger a spurious RdPulse.

Is there a race hazard (e.g., when the counter changes from 111 to 000)? And if so, how can I avoid it?

Answer 1

To avoid the possibility of the glitch, you might consider making the read signal a registered output. This will require some redesign of your state machine, since if you simply put a register in front of your AND gate, the read pulse will occur almost one clock cycle later than without the register. Therefore you will have to change the fan-in to your AND gate to select state 101 rather than what you currently have, which selects state 110. With this done, you may put a register in front of the AND gate clocked from the same clock as the counter. This will generate the read pulse at about the same time in the 8 state cycle as what you currently have but without the possibility of the glitch.

Answer 2

The 74LS273 is a D-type flip-flop which won't toggle.

You need to use J-K flip-flops (74LS73 or 74LS76) in toggle mode, i.e. J and K tied together and pulled high.

The output register can be a J-K flip-flop operating in D-type mode, i.e. using a NOT gate so that K equals not J. Or it can be a dedicated D-type (74LS273).

Something like this synchronous counter with a registered output:

Answer 3

Generally, using a ripple count is not a good idea if you care about skew and/or decoding the output.

So let's say you fix that. There's still the issue of inter-output skew and multiple outputs changing state, which can lead to glitches. There's several ways to address that:

• use a registered output for the decoded signal. Look ahead 1 state, decode that, then run it through a flop.
• Use gray-code count sequence. Gray-codes have the property of having one output at a time change state. This can be decoded without glitching.
• Use one-hot coding. Basically, dedicate a flop to each state. Then take the output of the one flop as your decoded signal.