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FPGAs have a reset signal that is spread across through the global routing. If the user logic needs to carry out a system reset for whatever reason, how should this be done?

Can the user logic actually drive the reset signal from itself which is ANDed with the reset coming from outside the FPGA? If so, what will happen with the routing resource usage?

Is there another way e.g induce the FPGA to reconfigure itself somehow like it does just after power-up?

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  • \$\begingroup\$ Do you want to reset the design or the device? Resetting the design would be done in your code directly based on whatever reset source you like; resetting the device would be done through some manufacturer-specific means, or by tying an FPGA IO pin to the dedicated reset input externally. \$\endgroup\$ – alex.forencich Dec 19 '20 at 5:53
  • \$\begingroup\$ I want to know how to do both, reset is a high fanout signal. If I want to reset the design, I will need a signal that is logically ORed with the system wide high fanout reset. But maybe this will create timing issues? I do not know if there are some important points to keep in mind when doing something like this or maybe it is recommended to not do this at all as it will create lot of work for the fitter. \$\endgroup\$ – Quantum0xE7 Dec 21 '20 at 6:17
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For Xilinx devices at least, the answers to your questions are all in Xilinx UG470 and UG953.
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug953-vivado-7series-libraries.pdf

FPGAs have a reset signal that is spread across through the global routing.

That's correct.

If the user logic needs to carry out a system reset for whatever reason, how should this be done?

It depends on what FPGA architecture you are using. For Xilinx parts pulsing the PROGRAM_B signal causes the part to reconfigure.

  1. You could physically put an AND gate on the board and tie one input to an external reset, and tie the other input to a GPIO pin. The GPIO pin needs a pullup resistor on it.

  2. You can use the IPROG command on the ICAPE2 primitive as documented in UG470 Table 5-19.

Can the user logic actually drive the reset signal from itself which is ANDed with the reset coming from outside the FPGA?

Yes, using the IPROG command. Or alternatively if you just want to reset the flip-flops without reloading the bitstream you can use the GSR pin on the STARTUPE2 primitive.

If so, what will happen with the routing resource usage?

Nothing. There is a dedicated global reset line in the FPGA, so additional routes are not needed.

Is there another way e.g induce the FPGA to reconfigure itself somehow like it does just after power-up?

Pulsing PROGRAM_B (by whatever method) causes a complete reconfiguration of the device.

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  • \$\begingroup\$ PREQ is an output, not an input. To trigger an FPGA reset, you have to load the IPROG command using the ICAP. \$\endgroup\$ – alex.forencich Dec 19 '20 at 5:50
  • \$\begingroup\$ @alex.forencich You are correct, I will change the answer to reflect that. \$\endgroup\$ – user4574 Dec 19 '20 at 20:50
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This no longer true on many modern FPGAs. Reset signals can be routed with large fanout signals like clocks, but many FPGAs don't have a dedicated reset circuit for this.

When I'm working with FPGAs I am very careful to only use reset signals when strictly necessary. If you're working with a state machine for example, you might just reset the state. Once it is in the correct state, the normal state machine operation will set all the outputs, so they don't necessarily need to be reset. It might take a few clock ticks to get to a totally known state, but that is alright.

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  • \$\begingroup\$ How to force reset than? \$\endgroup\$ – Quantum0xE7 Dec 19 '20 at 0:40
  • \$\begingroup\$ Yes they do. Microsemi have a devrst_b pin and colonic have a program_b pin.if these are pulled low for TBD then the fabric is reset \$\endgroup\$ – JonRB Dec 19 '20 at 12:05
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Do you want to reset the design, or the entire device?

Resetting the design is usually what you want to do. However, there are certainly applications for triggering a reset of the entire device. If you reset the design, in general there are things that cannot be reset (RAM contents, etc.), and you can reduce resource utilization by selectively resetting only the components that actually need to be reset, such as data bus valid signals (1 or 2 bits) and not the data bus itself (8, 32, 64, etc. bits). You can trigger a reset however you like, such as from an FPGA IO pin, the locked output of internal PLLs, etc. The tools in some cases will use a global clock net for routing high-fanout reset signals.

Resetting the whole device will trigger the device to reload the configuration. This only works if there is a flash device that the FPGA can read the configuration from, otherwise it after it is reset the device will sit idle waiting for a configuration to be loaded. Resetting the whole device will reload RAM contents and what not from the configuration bitstream. Triggering a whole-device reset is highly device dependent. One method is to externally connect an FPGA IO pin to the dedicated FPGA reset pin. Alternatively, there are usually ways to trigger a device reset without any external connections. For Xilinx devices, this generally means using an ICAP primitive to talk to the FPGA configuration logic and provide an IPROG command to trigger a device reset and reconfiguration. Note that it also can take a significant amount of time to read the configuration data from flash, so triggering a whole-device reset means the device will be out of commission of many milliseconds.

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