Do you want to reset the design, or the entire device?
Resetting the design is usually what you want to do. However, there are certainly applications for triggering a reset of the entire device. If you reset the design, in general there are things that cannot be reset (RAM contents, etc.), and you can reduce resource utilization by selectively resetting only the components that actually need to be reset, such as data bus valid signals (1 or 2 bits) and not the data bus itself (8, 32, 64, etc. bits). You can trigger a reset however you like, such as from an FPGA IO pin, the locked output of internal PLLs, etc. The tools in some cases will use a global clock net for routing high-fanout reset signals.
Resetting the whole device will trigger the device to reload the configuration. This only works if there is a flash device that the FPGA can read the configuration from, otherwise it after it is reset the device will sit idle waiting for a configuration to be loaded. Resetting the whole device will reload RAM contents and what not from the configuration bitstream. Triggering a whole-device reset is highly device dependent. One method is to externally connect an FPGA IO pin to the dedicated FPGA reset pin. Alternatively, there are usually ways to trigger a device reset without any external connections. For Xilinx devices, this generally means using an ICAP primitive to talk to the FPGA configuration logic and provide an IPROG command to trigger a device reset and reconfiguration. Note that it also can take a significant amount of time to read the configuration data from flash, so triggering a whole-device reset means the device will be out of commission of many milliseconds.