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STM32F4xx microcontrollers have 128KB of SRAM + 64KB of CCM SRAM. CMM SRAM is hardwired to data bus so it is impossible to use it with DMA.

  • What is the reason to add additional SRAM as CCM?
  • Does it increase performance and if that it's the case why it's so?
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2 Answers 2

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Let me point you to appnote AN4296 (for STM32F3). It talks about CCM in detail. It makes the distinction between Harvard and Von Neumann configurations.

The CCM is intended exactly for executing code at maximum speed. That may be interrupt handlers, but also ordinary functions.

There's a bus matrix. Both the CCM and ordinary SRAM have connections to data and instruction busses. The CCM has no connection to DMA because it's intended for code, which isn't ever supposed to be handled by DMA. It also features per-page write protection.

The thinking is that the core can fetch code from CCM while fetching data from the other SRAM at the same time. Different "busses" are used in parallel, giving you the best performance. If you fetch code and data from the same memory (either), it'll be slower because of contention.

Some STM32 have a thing called Adaptive Real-Time (ART) Accelerator. That's a cache on top of flash so you can execute "from Flash memory, with 0-wait states".

Even more recent STM32 (F7) have actual L1 cache on top of that.

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What is the reason to add additional SRAM as CCM?

The Cortex M3 and M4 Cores have 3 separate busses: Instruction, Data and "System". A transaction on one bus will not disturb other busses unless the same peripherial is accessed.

You already mentioned DMA. The DMA controller can only access a RAM when there is no concurrent access from the M4 core - and the core may need to wait for an ongoing DMA transfer to finish. So the CCM RAM can help to both increase performance and lower latency.

Not that code can be executed also from SRAM (but not CCM SRAM). Then you saturate the AHB just with fetching 32-Bit Thumb2 instructions. The CCM can take some stress from the Bus in this case - the prefetching would otherwise have to wait for data transfers.

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