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An FPGA can be interfaced with an ADC using CMOS or LVDS. Is there a way to use simulation to predict the power dissipation of the I/O blocks for a given operating frequency for this interface? If so, how can this be carried out?

Here we have an Intel MAX 10 and a Microsemi IGLOO2 being linked to a TI ADC. It would be great to be able to get a very reliable estimate for power dissipation between these two FPGAs when using LVDS and also when using CMOS, to interface with the TI ADC.

I am sure more information will be required to reach a complete answer.

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  • \$\begingroup\$ Yes. Some simulators allow switching power information to be dumped in a file and processed later by power estimation tools. Vivado makes this pretty easy, example. \$\endgroup\$
    – user16324
    Commented Dec 21, 2020 at 15:50
  • \$\begingroup\$ Here we have an Intel MAX 10 and a Microsemi IGLOO2 being linked to a TI ADC. It would be great to be able to get a very reliable estimate for power dissipation between these two FPGAs when using LVDS and also when using CMOS, to interface with the FPGA. \$\endgroup\$
    – gyuunyuu
    Commented Dec 21, 2020 at 15:52
  • \$\begingroup\$ Then Vivado won't help you very much. (You might want to add that info to the question, along with your Altera/Intel and Microsemi/Microchip doc searches. They must have something) \$\endgroup\$
    – user16324
    Commented Dec 21, 2020 at 15:56
  • \$\begingroup\$ I am sure that there is some way to do it although it is a mystery as of yet, lets see. \$\endgroup\$
    – gyuunyuu
    Commented Dec 22, 2020 at 0:22

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Intel's Quartus tools include both a "power optimization advisor" and a "power analyzer tool". The advisor says (among other things):

Choosing appropriate I/O standards can significantly reduce design power. To reduce power, use a low-voltage I/O standard (most important) and the lowest drive strength that will meet your speed requirements. For lower frequency applications or applications where I/Os are idle most of the time, I/O standards which are not resistively terminated, such as LVTTL, LVCMOS and PCI have the lowest total power, since they have very low static power. However, as I/O toggle rates increase these I/O standards eventually dissipate more power than resistively terminated standards such as SSTL, HSTL and LVDS, as the unterminated I/O standards generally have higher dynamic power. Use the Power Analyzer to analyze different I/O configurations and choose the lowest power option for your system.

So unless you're quite certain you're going to be reading from the ADC either very fast or very slow, that probably points toward using their power analyzer. At least as it shows up in the copy of Quartus Prime I use (under Linux) the Power Analyzer tool shows up on the "Processing" menu, and has a display like this:

enter image description here

As you can see, I've selected the part of its report dedicated to power drawn by the I/O section (though the design it has open in this case does almost no I/O, so the result it's showing is quite uninteresting).

The result it's showing right now is based only on compilation, but it can use data from simulation (preferably gate level, of course) to improve results.

I don't currently have Microsemi's tools installed, so I can't give any detail, but the last time I used them they had what I thought was a pretty decent power estimation tool as well (although I have to admit, most of what I've done in FPGAs has been much heavier on processing than I/O, so I don't have much personal experience with how well either does at estimating power drawn specifically by I/O).

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  • \$\begingroup\$ +1 of course, but maybe relevant from experience: I've had mixed results regarding the accuracy of the Intel tools, even when supplying simulation data. I can't rule out mistakes on my end when they turned out to be inaccurate, though, and I've seen them be spot on as well. \$\endgroup\$
    – DonFusili
    Commented Dec 23, 2020 at 7:34
  • \$\begingroup\$ @DonFusili: Yeah, exactly how accurate they are is a somewhat different question. What I'd personally like to see would be more capability for automatically finding sensitivity. I've seen people waste a lot of time on improving simulation of things that didn't really make any difference (and other places that a minor improvement in an estimate helped a lot). \$\endgroup\$ Commented Dec 23, 2020 at 8:56

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