Length matching is performed mainly to avoid the skew generated among the parallel data lines/data bus width.

All the high speed PCB design guideline suggest performing length matching with the clock trace length as the target length and trace length tolerance of the data, address, command lines has to be maintained with respect to clock signal. May I know the particular reason for this?

As I understand it, the clock appears continuously. There will not be any data loss in the clock, hence it is a periodic signal. Data will consider the positive edge or negative edge of the clock and it will appear initial sequence in the timing waveform.

Any insight would be greatly appreciated.

  • \$\begingroup\$ Just wondering: are you proposing to length match the clock lines to data +- multiples of the wavelength or are you asking if you can leave out matching at all? I've done the first and it's a bad idea but worked that time, the second can't work with reasons given in current answers. \$\endgroup\$
    – DonFusili
    Commented Dec 22, 2020 at 8:10
  • \$\begingroup\$ I also am wondering: are you asking why one should do length matching at all, or why the clock is taken as reference? I mean, perhaps you are asking why we do not take some random data line as reference, or maybe just have an external spec on the length? \$\endgroup\$ Commented Dec 22, 2020 at 8:43
  • 1
    \$\begingroup\$ @VladimirCravero, I am asking why the clock is taken as reference, instead of random data lines. \$\endgroup\$
    – Ananthesh
    Commented Dec 22, 2020 at 9:13

2 Answers 2


Data is sent in respect to the clock signal.

Data has to be stable before the clock edge (setup time) and it has to be stable after the clock edge (hold time).

If the clock wiring is too long compared to data, clock will appear too late to be within hold time specs, and if data wiring is too long compared to clock, clock will appear too early to be within setup time specs.


Every single signal is observed in relation to the clock; i.e. what matters for the receiver to "sample" all the parallel signals at exactly the right point in time, +- the allowable skew.

Example: Say, we have a bus where the allowable skew is +-50 ps, so that the receiver still gets the signals close to their maximum when it samples at the rising clock edge.

Now, it doesn't really help if all the signals have +-50 ps to each other, or say, to the first data signal – if data[19] has +40 ps delay to data[0], and data[0] has +20 ps delay to the clock, then data[19] has +60 ps delay to the clock and simply won't be sampled at the right time.


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