# T_hold and T_setup help me understand?

My exam is tomorrow and there is something I don't understand in the material, so I really hope to get some help with this.

Giving the following circuit:

And giving that both FF are connected to the same clock but FF2 gets it after a positive delay (t_skew after clock goes up) my professor said that this helps us in T_setup.

I understand this point since FF2 has more time to prepare itself for a new input to be processed, but what I don't understand is that why t_skew will be "harmful" when talking about T_hold?

• Your circuit doesn’t seem to follow accepted conventions, so it doesn’t communicate your intent. Nevertheless, with everything else being equal, moving the edge of your signal earlier than the clock helps setup but harms hold. Draw yourself a timing diagram and it should be evident. Commented Dec 22, 2020 at 15:57
• @Kartman already tried that but didn't help that much, I mean what is the different between setup and hold that it helps one and harms the other Commented Dec 22, 2020 at 17:02
• Hold time is the time an input must remain valid after the clock. If you delay the clock, and it now arrives after the input has stopped being valid, you clock garbage into the FF. That's why positive clock skew harms hold time.
– user16324
Commented Dec 22, 2020 at 19:03

what I don't understand is that why t_skew will be "harmful" when talking about T_hold?

Hold violation happens when the data launched by FF1 reaches FF2 "too earlier" than it is supposed to be.

Suppose a data was launched by FF1 on the clock edge at a time $$\t\$$. After a clock skew of say $$\\Delta t\$$, the same clock edge reached FF2 at $$\t+\Delta t\$$. In this clock edge, FF2 has to capture the data launched by FF1 on the previous edge (ie., the clock edge just before $$\t\$$, not the one at $$\t\$$). Just like any flip-flop, FF2 also has a Hold time $$\t_{hold}\$$. So what $$\t_{hold}\$$ says is that, for a data to be properly captured by FF2, the data has to remain valid for $$\t_{hold}\$$ time after the clock edge appeared at FF2 (assuming setup has already met). Now imagine, if the data launched by FF1 at $$\t \$$ has already 'traveled' through the combinational path and reached FF2 within this time window. This will now corrupt the "previous" data which is supposed to be the data captured by FF2 in this clock edge at $$\t+\Delta t\$$. FF2 is now said to be driven to metastability This is called Hold violation.

Intuitively, in the above scenario, the probability of Hold violation could have been reduced:

• If combinational delay between FF1 and FF2 was higher, because the data launched by FF1 now arrives a bit late at FF2.
• If clock skew $$\\Delta t\$$ was lower, because the clock edge appears a bit early at FF2.

The same idea can be analyzed mathematically if you write down the equation for satisfying Hold at FF2 - $$t_{Clk-Q-FF1}+t_{combi}\ge t_{hold}+\Delta t$$ $$\implies (t_{Clk-Q-FF1}+t_{combi}-t_{hold})\ge \Delta t \tag 1$$

As you can see, for a constant value at the LHS, if the RHS increases, then the chances of violating this equality condition increases. Hence the conclusion - if the clock skew increases, it is 'bad' for hold timing.

• Thanks, Unrelated please see: electronics.stackexchange.com/questions/537372/… I think I found a bug in your solution Commented Dec 22, 2020 at 23:47
• I read it. Your calculations are wrong. Commented Dec 23, 2020 at 3:13