I want to connect an AD7626 with a Zynq FPGA or a Kintex. Which bank should I choose?

Let say the for case

  1. Chosen Zynq FPGA has only HR bank
  2. Kintex has HR and HP bank.

How should I choose a bank for both of these cases? What are the things one should look at in the ADC datasheet when an FPGA needs to be connected? How should one choose an FPGA bank in this case? Does this depend on the supply voltage for the ADC?

From different forums I understood I should check if the DC characteristics of the LVDS input and output of the ADC are within the range specified in the FPGA datasheet, but could not find how to choose a bank.

##Details of ADC are as follows##

  • Differential Output Voltage, VOD 245 to 454mV
  • Common-Mode Output Voltage, VOCM 9802 to 1375mV
  • Differential Input Voltage, VID 100 to 650 mV
  • Common-Mode Input Voltage, VICM 800 to 1575 mV
  • \$\begingroup\$ It's not trivial to design a system that interfaces an FPGA and an ADC. Can you give details of your application? \$\endgroup\$
    – David
    Commented Dec 22, 2020 at 18:09
  • \$\begingroup\$ weight measurement/ calibration is the application...but thats not important.. i want to understand this physical Connection between adc and fpga \$\endgroup\$ Commented Dec 22, 2020 at 19:20
  • \$\begingroup\$ How are you supplying the sample clock to the ADC? \$\endgroup\$
    – David
    Commented Dec 23, 2020 at 20:07

1 Answer 1


Here are the things to consider.

  • All the IO in one bank must use the same supply voltage.

  • You must pick a supply voltage for which you are allowed to choose LVDS as the IO standard.

  • If you have other pins already in an IO bank, then you can only put your LVDS signals on that bank if the other IO is also able to work with the same supply voltage.

To learn more about the IO on the 7-series devices consult UG471.

Per page 91, the LVDS standard is only available in the HP IO banks when powered at 1.8V, and the VDS_25 standard is only available in the HR IO banks when powered at 2.5V.


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