I have a counter (74HC193) counting up with Qn outputs being decoded by a demultiplexer (74HC138). My clock pulses (CP) are no less than 100 microseconds long and the interval between them is always greater than that. The counter counts on the rising edge of CP. I disable the output of the demultiplexer when CP is high by directly tying CP to the not-enable input of the demux, to avoid random/spurious demux outputs from going true while the counter outputs are in transition.
This seems to work well enough however I am aware of the race condition between the counter outputs changing and the demux output being disabled quickly enough (by CP rising to high). I want to ensure that a spurious output on the demux never happens, given that CP rising is also what causes counting. The outputs from the demux are used sometimes to cause latches to latch and unlatch, and those devices (eg. 74HC74) respond to very narrow pulses, which entirely explains my worries.
I have read the Texas tome on slow or floating CMOS inputs, and datasheets describing propagation times and so forth and I am not finding myself competent enough to penetrate all that without going back to college. It is important to me to not expand the number of packages in my circuit, if I can at all avoid it. Adding a two-phase clock, for example, would be going too far.
My instinct is to just slow something down with a series resistor, either counting on the natural capacitance and high impedance of a CMOS input alone, or by adding some extra capacitance. I only need enough of a delay to solve the potential problem described above. Delaying the clock input to the counter seems the most likely route to me; but then I read the aforementioned tome from Texas and had a doubt. An RC solution slows down the signal, and any delay is just a consequence of that.
I also thought of simply immunising the inputs of any latches with a similar RC solution, and that is something I would like to do anyway.
So any general wisdom on slowing down or delaying CMOS logic input signals will be greatly appreciated as well as any on this specific scenario.
I should add that for sure my circuit will suffer from excess lengths of connections, random idiosyncratic sloppy design features by yours truly, and lots of other bad things. This is partly why I am looking for a little bit of an extra security blanket with this race condition thing. I should also add that I don't anticipate counting frequencies much higher than, say, 10KHz. (which is why I don't mind slowing some things down, if feasible)
I should also add that between CP and the clock input (CPu) there are already a couple of gate delays through separate packages (74HC04 and 74HC00), and there are a couple of spare inverters laying around that could be given a mission.