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We were told in class that although in theory we can have multiple-input logic gate and therefore can get a two level implementation of functions, it is practically not possible. I don't really understand why this is the case.

For example, if we take a 3 input AND gate (to implement F = xyz', say), it would have 3 MOSFETs in parallel and 3 in series, causing a delay of 3N (if N is the delay of each transistor.

Now instead, we only have 2 input gates available, and we implement w = xy' first and then F = zw, we would have a delay of 2N + 2N = 4N instead.

Clearly, the higher input AND gate is superior in terms of delay. What disadvantage do multi input gates possibly have that result in them not being used practically?

TIA

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  • \$\begingroup\$ Repeat that line of reasoning with a 4 input gate... incidentally I can buy an 8 input gate, but I can't recall seeing anything larger. \$\endgroup\$ – Brian Drummond Dec 24 '20 at 17:26
  • \$\begingroup\$ @Brian So if I compare 4 input vs 2 input, delay for 4 inputs would be 4N, while using three 2 input gates would result in 3*2N = 6N \$\endgroup\$ – user_9 Dec 24 '20 at 17:34
  • \$\begingroup\$ Remember that MOSFETs do not behave like ideal resistors. You must also consider the parasitic capacitances and the body effect. \$\endgroup\$ – Elliot Alderson Dec 24 '20 at 17:41
  • \$\begingroup\$ @user_9 Three 2-input gates would only be two gate delays, not three, if you arrange them properly. Find ab = x and cd = y in parallel, then take xy = z for your output. \$\endgroup\$ – Hearth Dec 24 '20 at 17:46
  • \$\begingroup\$ @Hearth ah got it, my bad. \$\endgroup\$ – user_9 Dec 24 '20 at 17:51
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Individual gates are made up of series or parallel combinations of n or p channel transistors. The delay through the transistors is proportional to the total resistance of the transistors. This is worst case in CMOS technologies when you have a number of P channel transistors in series. Size for size P channel transistors have about 3 times more resistance than N channel. If they are all series you have a NOR gate.

schematic

simulate this circuit – Schematic created using CircuitLab

The gate designer will attempt to increase the width of the P transistors in order to keep the rising propagation delay down. At some point it becomes more economical to use multiple gates to increase the effective number of inputs rather than increasing the transistor size in one gate.

This trade-off depends on the technology used but for CMOS it is generally in the range of 4-6 inputs.

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Repeat that line of reasoning with a 4 input gate...

So if I compare 4 input vs 2 input, delay for 4 inputs would be 4N, while using three 2 input gates would result in 3*2N = 6N

As shown on the left here.

schematic

simulate this circuit – Schematic created using CircuitLab

Arrange them as a tree; 2 gates processing 4 inputs, the third combines their results. Each 2 input gate has delay 2N, the overall delay is 4N matching the 4 input gate (middle example)

Now repeat for 5 and more inputs : 5 inputs has a tiny advantage, 5N delay with a direct implementation, or 6N with the structure on the right. But perhaps you can see that at 8 inputs, the direct implementation is actually slower (8N) than the 6N implementation on the right.

So it's not that higher gates are difficult or impossible; it's that there's no general advantage, and in many cases the result is slower than a tree of 2 input gates.

Incidentally I can buy an 8 input gate (74LS30), but I can't recall seeing anything larger (though a 13-bit gate, 74LS133, is mentioned in the comments)

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    \$\begingroup\$ 74LS133 and variants are 13 input nand gates: (ti.com/lit/ds/symlink/…). \$\endgroup\$ – Kevin White Dec 24 '20 at 18:24
  • \$\begingroup\$ Interesting to note that LS133 has almost the same propagation delay (10ns) as LS00 low to high, but 4 times longer (40ns) high to low. \$\endgroup\$ – Bruce Abbott Dec 26 '20 at 3:53
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There is a limit because any additional input requires an additional transistor and there is some voltage drop on the transistor which for a large number of transistors will be equal to the supply voltage.

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  • \$\begingroup\$ That's not actually true – you'd need one or two transistors to regenerate the signal to "full" levels. A transistor is much, much smaller than the contacting pad for another input, so that's really not the reason. \$\endgroup\$ – Marcus Müller Jan 7 at 16:40

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