We were told in class that although in theory we can have multiple-input logic gate and therefore can get a two level implementation of functions, it is practically not possible. I don't really understand why this is the case.
For example, if we take a 3 input AND gate (to implement F = xyz', say), it would have 3 MOSFETs in parallel and 3 in series, causing a delay of 3N (if N is the delay of each transistor.
Now instead, we only have 2 input gates available, and we implement w = xy' first and then F = zw, we would have a delay of 2N + 2N = 4N instead.
Clearly, the higher input AND gate is superior in terms of delay. What disadvantage do multi input gates possibly have that result in them not being used practically?