6
\$\begingroup\$

The whole PCB layout is as the picture below (haven't poured polygon to GND). I have some puzzlements about power trace routing.

My teacher told me if the power trace is placed like a circle or half circle, it will become an inductance which might make the PCB not work.

  1. I don't know if my power routing makes a circle. Could you please help check if my PCB routing has this issue?

    enter image description here

  2. The input 3V3 trace of top layer (red) is connected to the bottom (blue) by a via, the angle of red trace and blue trace is below 90 degrees. Is this kind of routing right?

    enter image description here

\$\endgroup\$
3
  • \$\begingroup\$ Straight traces have inductance also. I don't see anything bends that will alter that significantly. What frequency does this circuit operate at? \$\endgroup\$
    – Mattman944
    Dec 25, 2020 at 3:30
  • \$\begingroup\$ @Mattman944 It's just a 7-segment clock display PCB example.the frequency is low. \$\endgroup\$ Dec 25, 2020 at 3:52
  • \$\begingroup\$ @user7476499 Just a note that on a PCB we generally refer to the copper not as a "wire" but as a "trace" or "track." \$\endgroup\$
    – JYelton
    Nov 5, 2021 at 15:25

1 Answer 1

9
\$\begingroup\$

Consider that all of the power pins of the DFN(?) chip are probably connected to each other by metal on the chip itself.

Now you have one trace leading up around the left side of the chip to its upper right corner. And another leading around the bottom of the chip to its lower right side. And then, probably a trace within the chip itself connecting those two wires.

So yes, you probably have created a loop in the 3V3 net.

Conceivable this could generate or receive radiated signals as if it were a loop antenna.

The odds of this actually causing a circuit failure seem fairly low, assuming the chip in question is a simple digital chip of some kind operating at 100 MHz or lower. But still it would be better practice to eliminate this loop.

If this is a sensitive analog chip or a very high speed digital chip (100's of MHz or GHz) then I'd strongly recommend eliminating the loop.

I'd also recommend providing a bypass capacitor near every power pin of the chip.

\$\endgroup\$
2
  • \$\begingroup\$ I have drawn 4 decoupling capcitors on schematic which is recommended place as close to every 3.3V pin as possible.Because the power and GND is most used wire,I place them at last.But at last the capcitor can't be that close due to other component.How to deal with this issue?Widen the wire? \$\endgroup\$ Dec 25, 2020 at 11:52
  • 1
    \$\begingroup\$ Can you put the decoupling caps on the other side of the PCB, below the IC? One tip for decoupling caps: Not only the positive lead should be as short as possible, the ground wire matters just as much. Try to minimize the sum of positive wire length and ground wire length. \$\endgroup\$
    – Michael
    Dec 25, 2020 at 15:44

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.