Consider that all of the power pins of the DFN(?) chip are probably connected to each other by metal on the chip itself.
Now you have one trace leading up around the left side of the chip to its upper right corner. And another leading around the bottom of the chip to its lower right side. And then, probably a trace within the chip itself connecting those two wires.
So yes, you probably have created a loop in the 3V3 net.
Conceivable this could generate or receive radiated signals as if it were a loop antenna.
The odds of this actually causing a circuit failure seem fairly low, assuming the chip in question is a simple digital chip of some kind operating at 100 MHz or lower. But still it would be better practice to eliminate this loop.
If this is a sensitive analog chip or a very high speed digital chip (100's of MHz or GHz) then I'd strongly recommend eliminating the loop.
I'd also recommend providing a bypass capacitor near every power pin of the chip.