1
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Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear as shown in ASIC.CO.IN:

module counter (clk, clr, q);
input        clk, clr;
output [3:0] q;
reg    [3:0] tmp;
always @(posedge clk or posedge clr)
begin
   if (clr)
      tmp <= 4’b0000;
   else
      tmp <= tmp + 1’b1;
end
   assign q = tmp;
endmodule

    

Can I define the output as reg and write the verilog as following?:

module counter (clk, clr, q);
input        clk, clr;
output [3:0] q;
reg    [3:0] q;
always @(posedge clk or posedge clr)
begin
   if (clr)
      q<= 4’b0000;
   else
      q<= q+ 1’b1;
end

endmodule

    

As I see this, there is no difference between those two codes, am I wrong?

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1
  • \$\begingroup\$ Yes, they are equivalent. \$\endgroup\$
    – Light
    Dec 25 '20 at 8:23
3
\$\begingroup\$

There is no difference in the two examples you wrote. You can even make is simpler:

module counter (
  input  wire clk, clr,
  output reg [3:0] q
);
always @(posedge clk or posedge clr)
begin
   if (clr)
      q<= 4'b0000;
   else
      q<= q+ 1'b1;
end

endmodule
\$\endgroup\$
0
0
\$\begingroup\$

If it is anything like VHDL older than VHDL 2008, it is because you cannot read an output (you can only write to an output), and performing something like q<=q+1 requires you to read q.

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1
  • \$\begingroup\$ please check the following, which is the Verilog code for flip-flop with a positive-edge clock. module flop (clk, d, q); input clk, d; output q; reg q; always @(posedge clk) begin q <= d; end endmodule as you can see, output as register can be written \$\endgroup\$
    – Zohar
    Dec 25 '20 at 8:40

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