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I'm watching a lecture on designing pipelines in HDL, and it's mentioned that the buffers (for intermediate values) between pipeline stages should be master-slave flip flops to avoid race conditions. Why is this preferable to common edge-sensitive D flip flops? Looking at other places where similar questions were asked, I find answers of why the T operation in JK flip flops causes a race condition (not relevant to D flip flops) or why a master-slave D flip flop must be used instead of a D latch (obvious). What are the differences between a standard edge-triggered D flip flop and a master-slave D flip flop and why is the latter preferable?

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  • \$\begingroup\$ A standard edge-triggered D flip flop is a master-slave D flip flop. I don't understand why you think they are different. \$\endgroup\$ Dec 27, 2020 at 14:45
  • \$\begingroup\$ Per Wikipedia a classical positive-edge-triggered D flip-flop uses three ~SR NAND latches. I do not know if there is any meaningful difference between them. \$\endgroup\$ Dec 28, 2020 at 10:57
  • \$\begingroup\$ @ElliotAlderson that is not true; a MS flop made with two D flops, one of which is fed the negated clock. See here. \$\endgroup\$ Dec 28, 2020 at 12:40
  • \$\begingroup\$ @VladimirCravero No, a MS flip flop is made with two D latches. \$\endgroup\$ Dec 28, 2020 at 13:06
  • \$\begingroup\$ @JustinOlbrantz A "classical" flip-flop might be constructed from SR latches (usually just two) but that's not how they are actually built in modern CMOS circuits. \$\endgroup\$ Dec 28, 2020 at 13:08

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When you are building a pipeline, you need to introduce a delay in the datapath - that is basically what a pipeline does.

If you use "naked" D flops, they will all change their output on the same clock edge. Assume you have a D flop barrier, your combinatorial logic, and then another barrier: this is your basic pipeline building block. When the clock edge comes, the input and output barriers sample their input, and immediately present it at their output. This means that there is the possibility that the input of the output barrier will change while it is sampling it, possibly violating hold times.

If you instead use master slave flops, this does not happen, as the input is sampled on one edge, and copied to the output on the opposing edge.

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    \$\begingroup\$ I'd think we can add that this is merely a concern with slow and discrete pipelines using ideal FF. In real-world high-speed pipelines a MS-FF is worse, because it reduces the achievable frequency - the setup/hold time issues can be addresses by tuning the physical implementation of the FF to get a negative hold time and a larger CLK-to-Out time. \$\endgroup\$
    – asdfex
    Dec 27, 2020 at 9:50
  • \$\begingroup\$ You have exactly the same problem with a master-slave flip-flop as the end of the sampling time. is at exactly the same time as it transfers the data to the output - it just happens to be on there negative edge. Nobody uses "master-slave" flip-flops in a pipeline logic system. You always have to abide by the hold time - conveniently many D-flip-flops have zero hold time. \$\endgroup\$ Dec 27, 2020 at 18:08
  • \$\begingroup\$ The point to use an MS flop is that the input of the whole thing is sampled on one edge, and the output is changed on the opposing edge, so that the following combinatorial logic and flop barrier has almost half a period to settle. \$\endgroup\$ Dec 28, 2020 at 8:30
  • \$\begingroup\$ Does a master-slave D flip flop really change its output on the opposite edge it reads its input? I can see that on the opposite edge the second latch latches the value for output, but it looks to me like the triggering edge causes the first latch to latch the input and the second latch to go transparent, which would mean the output changes on the same edge the input is read, with a bit of propagation delay due to the inverter. \$\endgroup\$ Dec 28, 2020 at 11:18
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    \$\begingroup\$ @JustinOlbrantz please see here. A MS flop is two D latches, one of which is fed the negated clock. \$\endgroup\$ Dec 28, 2020 at 12:38

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