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I encountered some questions and problems I asked myself lately and hoped I can get a nice lead here before I start reading long articles without even be sure if it's the right way.

Let's assume I have an FPGA design, where I get ADC data with a sampling rate of 40MHz, so I latching the data from the ADC interface in 40MHz.
but I want to make the DSP inside the FPGA in 100MHz clock speed (for example because I have DDR3 memory interface in the DSP block diagram which working in 400MHz in 4:1 clock rate that means the UI clock of the DDR3 is 100MHz).
The data from the ADC interface which coming in 40MHz rate is 90% of the time valid, which means I need most of it.

So the first question I want to ask, How would you move the data stream from the slow to fast clock domain?
I already made a working mechanism for this, I filled up a FIFO (with 1024 depth) and right after that start to fill the next FIFO ( I used 2 FIFOs),
while the Reading process from the first FIFO starting at the moment the first FIFO is filled, and from this time on, I just read the 1st and then 2nd and 1st and 2nd and so on... while keep to writing to the 2 FIFOs each at a time.

After I finished to write this block, I asked myself if there is a better way,

I encountered the Interpolation filter using FIR, does Interpolation make this job of moving from slow to fast clock domain for a stream of data?

I also saw the Polyphase filter which seems like also a way to move to a faster sampling rate.

Does its filter which easy to instantiate in FPGA is the right way to move the stream of data to a faster clock domain, or my way with FIFOs is the way to go?
thanks.

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  • \$\begingroup\$ this is the wrong section, you need to go to the superuser section or signal processing, or hardware recommendation :) but I do interested in your superb question. are you want to build DIY FPGA? or do you create analysis build? \$\endgroup\$ Dec 28 '20 at 7:46
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    \$\begingroup\$ @XCSource I get a lot of help in this section regarding FPGA design, I don't think anyone in Signal Processing will know how to answer it. Because it more of an FPGA design question than DSP. in DSP term the answer is just to do an Interpolation filter and you will get greater MSPS for your signal -> but I more interested in the FPGA design perspective answer. \$\endgroup\$ Dec 28 '20 at 7:50
  • \$\begingroup\$ What are you actually trying to accomplish here? Is there a reason you want a 100 MSPS version of the signal? Or do you just want to use your 100 MHz logic to stash the 40 MSPS samples it in the DDR? Those are nearly completely different goals. \$\endgroup\$ Dec 28 '20 at 8:10
  • \$\begingroup\$ @ChrisStratton I want to use 100MHz clock to processes the data, one of the reasons for it is because it more convenient to pass and receive data from the DDR module using 100MHz clock but not only, also to make data processing faster inside the FPGA \$\endgroup\$ Dec 28 '20 at 8:12
  • \$\begingroup\$ Then do so. Logic/processor clock speed need not be locked to sample rate (you certainly do not need to resample), it needs to only be sufficient to keep up with the flow of data if it is happening in realtime. \$\endgroup\$ Dec 28 '20 at 8:15
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So the first question I want to ask, How would you move the data stream from the slow to fast clock domain? I already made a working mechanism for this, I filled up a FIFO (with 1024 depth) and right after that start to fill the next FIFO ( I used 2 FIFOs),

Exactly like you're doing it: with clock domain crossing FIFOs.

After I finished to write this block, I asked myself if there is a better way, I encountered the Interpolation filter using FIR, does Interpolation make this job of moving from slow to fast clock domain for a stream of data?

No. I mean, yes, but no.

You want to pass the same samples on to a faster clock, and process them there. Interpolation (and all resampling) actually change the digital signal.

Let's illustrate with an example: Say you want to go from a 40 MHz-sampled signal to 200 MS/s (megasamples per second). What you do is simply insert 4 zeros after each input sample. Because you usually want the "zeros" to not be zeros but represent the analog signal as if it was sampled at 200 MHz to begin with, you apply a low-pass filter (in that application it's called an anti-imaging filter) and get an interpolated signal.

Just because you get 200 million samples per second, however, doesn't mean you need to process them at a throughput of 200 million samples per second, or at a 200 MHz clock rate. You can process them as fast as you want, and if you have enough buffer, also as slow as you want.

Sampling Rate and Clock Rate are not inherently linked.

Think about this in your PC: say, you have an raw PCM audio file, sampled at 44.1 kS/s. You want to encode it as MPEG 4 audio; although the piece of audio might be minutes long, the encoding process takes only seconds: it isn't necessary to bring the audio file to the "processing rate" of your CPU (whatever that rate might be – it really doesn't exist).

Same for your FPGA domain: sure, your higher-clock-domain logic will probably have to idle in between if it's fed samples from a lower-speed ADC, but that just means you can relax, and it's OK if things take more than one clock cycle per sample to work.

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