I try to build a radiation detector using of an arrangement of silicon photomultipliers (SiPMs) coupled to a scintillator and I want to read out the number of photons recorded by each SiPM sensor. I need to build a data acquisition system to store the recorded SiPM signals on disk, so that I can analyze them on my PC later. I expect event rates of around 10³ - 10⁴ events per second, where each true event generates a signal in several sensors at the same time. The rate per sensor is probably an order of magnitude smaller.
There are many academic publications dealing with the simultaneous readout of many individual SiPMs. However, these are mostly state-of-the-art experiments using high-end customized ASICs and VME crates, which are out of my reach. This is more of a hobby project and I do not have advanced equipment at my disposal. Therefore, I would like to build the readout chain with parts I can buy off the shelf. But I am unsure how to do this exactly and have some questions:
Is it realistic to attempt to create a multichannel SiPM readout at home with off-the-shelf components or is this too ambitious? Ideally, I would like to use parts I can either plug into a prototype board or solder manually, but especially some of the high-performance components (like a multi-channel high-speed ADC) mainly come in compact packages. Is it feasible to use evaluation boards to use such components?
Does the following readout chain seem like a reasonable approach or am I missing something important?
- A simple bias voltage supply for the SiPMs
- A shaping and amplification stage for each of the SiPMs to extract and form the signals
- Digitization of the signals with a high-speed ADC
- Feeding the digitized signals into an FPGA, where discriminator and trigger conditions are defined
- Sending the accepted events to a PC, where they are stored for later evaluation
I'll probably start with a small number of SiPM sensors, but the goal is to use a large number of sensors simultaneously (I am envisaging 64 or more). I think this will be challenging and the above steps will become more complicated. I guess this would require a number of FPGAs working in parallel and then some coordination between them. Are there established ways how to handle a very large number of inputs?
Thank you in advance for your suggestions!
Note: This is an edited version of my original question to be more specific