0
\$\begingroup\$

I'm examining a chip die and I'm trying to figure out what this arrangement of transistors is equivalent to if it's a logic gate or what (something you could get in a 74LS chip for example).

schematic

simulate this circuit – Schematic created using CircuitLab

\$\endgroup\$
5
  • \$\begingroup\$ Is this homework? Can you otherwise explain how you got a die photo and precisely identified the FETs and their interconnection with 100% confidence, without being able to recognize their purpose? Could you solve this if only one of the input FETs were present? If only two? \$\endgroup\$ Commented Dec 30, 2020 at 21:59
  • \$\begingroup\$ Not homework, just quarantine boredom -_- It's a die shot of a 6502 variant, which is already a very complex yet transistor-efficient design. My first step to making a 6502 in TTL logic chips is turning the transistors into gates. This one appears frequently throughout \$\endgroup\$
    – zvolk4
    Commented Dec 30, 2020 at 22:01
  • \$\begingroup\$ That seems like a sufficiently impractical approach that it will likely not work; if you were going to design a CPU you'd do so to the architectural model, not the in-the-weeds logic as different technologies make different schemes sensible. Anyway, as before, remove parts until you get something simply enough that you can recognize and then add them back in. If the source of T2 were grounded, what would it be? If T4 were missing what would it be? If T2 were a piece of wire what would it be? So what is the combination? \$\endgroup\$ Commented Dec 30, 2020 at 22:05
  • \$\begingroup\$ T1 is just a constant current pull-up. T2, T3 and T4 are all Nmos so you can think of them as if they were switches which close when a logic "1" is applied. Hint, it's actually a couple different gates wired together \$\endgroup\$
    – Sam
    Commented Dec 30, 2020 at 22:08
  • 2
    \$\begingroup\$ Well I'm a dope. I might as well delete this post for this lol - I used a LOGIC TABLE. works like magic. I think it's equivalent to the expression { ~D = A and (B or C) }. Sam was right that it's two gates - yet only four transistors. Those engineers at MOS really did the most to optimize their CPUs, that's for sure. \$\endgroup\$
    – zvolk4
    Commented Dec 30, 2020 at 22:10

0

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.