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I'm looking at the datasheet for a non inverting CMOS buffer CD74HC4050 What is the lowest voltage that can be placed on 1A to cause 1Y to be logic High? I know it's somewhere in the datasheet but I new to this and don't know which value. Thanks

Datasheet https://www.ti.com/lit/ds/symlink/cd74hc4050.pdf?ts=1609459927711&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FCD74HC4050

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  • \$\begingroup\$ So far, people are answering assuming you mean: What is the lowest voltage that can be placed on 1A to guarantee 1Y to be logic High? When the input is between about 30% and 70% the output is technically undefined, although the threshold is typically 50% for CMOS. So, the anal answer is 30%, but I don't think that is what you want. \$\endgroup\$
    – Mattman944
    Jan 1 at 1:28
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You are looking for the minimum value of Vih: enter image description here

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3.15 V is the Vih value when the chip is powered bu 4.5 V. For both the 4.5 V and 6.0 V cases, the input threshold level is 70% of Vcc. So ... I say that at 5.0 V the minimum input threshold voltage is 3.5 V, not 3.15 V.

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CMOS is designed so that Nch and Pch thresholds are matched so the threshold is Vdd/2.

Due to Mfg tolerances and thermal sensitivity, this data sheet defines the guaranteed thresholds as about +/-25% of Vdd/2.

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  • \$\begingroup\$ This answer with tolerances is correct. Vih and Vil are a ratio metric wrt.Vdd Ignore the troll-1 \$\endgroup\$ Jan 3 at 22:14

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