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I am challenging myself to create an analog voltage storage device. I came up with some ideas and I would like some inputs on what is bests and maybe new ones.

Ideally, I could store a voltage in a capacitor (electrolytic) and that's it. However, nasty leak currents and parasitic effect will result in a slow but inexorable drop in capacitor voltage.

Let's try with the easy one first:

  1. Connecting the capacitor to a 1 MΩ resistance to the power supply. It is a wild assumption that the leak current will be the same across the Capacitor voltage but it would at least reduce the discharge effect. PROS: Simple, effective. CONS: it will slowly charge/discharge the capacitor above/below a certain Voltage depending on the internal resistance.

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  1. Use an op-amp to read the cap voltage, compare it with a second capacitor and push current to both capacitor if there is a drop (recharging both caps with one current burst). PROS: will compensate the cap Leak across all voltages. CONS: complex and requires fine tuning to avoid positive feedback. I want to store the voltage in the 1 μF capacitor.

enter image description here

  1. Use of integrator: Kind of same as option 2. I want to store the voltage in the 1 μF capacitor.

enter image description here

  1. Another idea is to use an op-amp as Leak Current detector and cause a proportional voltage response to recharge the cap for the exact same charge (need still to figure out the details.)

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Any other suggestion?

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    \$\begingroup\$ Useful search term : sample and hold. \$\endgroup\$ Jan 1, 2021 at 21:18
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    \$\begingroup\$ Also called "track and hold"; related: electronics.stackexchange.com/questions/312463/… \$\endgroup\$
    – MarkU
    Jan 1, 2021 at 22:15
  • \$\begingroup\$ There's been some research into using EEPROM cells (floating-gate MOSFET structure) as analog charge storage elements: cecs.uci.edu/~papers/compendium94-03/papers/1995/islpd95/… and also ieeexplore.ieee.org/document/137321 -- though it may be unobtainium without designing a custom ASIC in an EEPROM process. Not sure how well it would work with commercial off-the-shelf EEPROM chips. Might be simpler to use an ADC to digitize the analog value, then use a DAC as the output driver (though that violates your 'only analog components' criteria) \$\endgroup\$
    – MarkU
    Jan 1, 2021 at 22:33
  • \$\begingroup\$ I think the best bet is to use a very low leakage capacitor. I think it will be hard to surpass that. Maybe an extreme low input leakage op-amp voltage follower can servo the voltage into a larger more leaky cap. \$\endgroup\$
    – mkeith
    Jan 2, 2021 at 1:44
  • \$\begingroup\$ Thanks! Sample and Hold still rely on a capacitor to "hold" the voltage, but it seems Polypropylene capacitor may have low enough leakage current to hold a voltage for days. \$\endgroup\$
    – Markhaus
    Jan 4, 2021 at 9:42

2 Answers 2

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Way back in the 60's before FETs and digital logic were common, the best way (in fact, pretty well the only practical way) to store analog voltages was to use a servo-driven potentiometer. It was slow, cumbersome and expensive, but it didn't drift and could store for an indefinite time.

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  • \$\begingroup\$ Thanks, indeed it seems the most reliabale way, even though is bulky as you mentioned. \$\endgroup\$
    – Markhaus
    Jan 4, 2021 at 9:40
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You could try a small telecom style relay as a switch and use an ultra-low input bias current op-amp. Be sure to limit the maximum charge/discharge current so the contacts are not damaged.

At room temperature, with low humidity, good construction practices, and with a lucky op-amp unit you might get an input bias current of a fA or less. Or maybe a few fA, but in that range, depending.

A good 1uF polypropylene capacitor might have a leakage resistance in the several x \$10^{13}\$ ohm range. If you charge the cap to 10V the leakage represents a time constant of somewhere in the 1 year range and a bias current of 3fA contributes +/-10% or so to that.

So you could store a voltage on there and it might be able to remain stable to +/-1% for several days.

Bob Pease (and maybe Jim Williams) wrote some good app notes and trade rag columns on this subject in the past. You can have fun and look them up. Things like using a PTFE standoff for the critical node can make a difference.


Or, more practically, you could just read the voltage with a 10-bit ADC, store it in an EEPROM and spit it out to a DAC, and it could stay within 1% indefinitely. We used to make controllers with time constants in the 1 hour range with analog parts, but digital certainly has advantages when times get long.

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    \$\begingroup\$ "Or, more practically, you could just read the voltage with a 10-bit ADC, store it in an EEPROM "- but that's not ONLY analog components. \$\endgroup\$ Jan 2, 2021 at 5:48
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    \$\begingroup\$ @BruceAbbott Yes, that is correct. \$\endgroup\$ Jan 2, 2021 at 5:49
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    \$\begingroup\$ Here is some Bob Pease on the topic of capacitor leakage. electronicdesign.com/technologies/analog/article/21801224/… \$\endgroup\$
    – mkeith
    Jan 2, 2021 at 7:29
  • \$\begingroup\$ Thanks a lot for the input! \$\endgroup\$
    – Markhaus
    Jan 4, 2021 at 9:40

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