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What is the input impedance of a typical MCU ADC? In this case I'm working with a PIC24FJ64GA004. I don't need high speed sampling - a maximum of 100 samples per second.

I wish to connect a resistive divider with a 100k resistor and a 10k resistor, so the impedance should be higher than 1M or else the impedance will start skewing the readings.

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  • \$\begingroup\$ Input impedance is not what you should worry about at a 100 Hz sample rate with a sub-megaohm source, but things like aliasing or capturing transients (if it even matters). \$\endgroup\$ – Nick T Oct 22 '10 at 14:30
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Input Leakage Current

To determine your resistors voltage drop from the gate you need to use the leakage current from the datasheet. Microchip specifies an "Input Leakage Current" on their datasheets. The datasheet that I have looked up specifies an input leakage current of 1uA. This could cause a .1V or 100mV, which is only double what robert calculated, probably not a problem on your signal.

Now remember, if you are dividing a 30V signal down to 30/11(2.7v) volts full read then the 100mV is added to this, causing up to 3% error on your 30V signal.

If you need a resolution of 1V, divide that by 11 and then add the 100mV. This 100mV could be larger then the 1V signal.

Input Capacitance

Robert is correct, there will be a capacitance, but this really specifies an amount of time that is needed to take the ADC measurement. This also, combined with your input resistance you chose, creates a low pass filter, if you ware wanting to measure signals with a higher frequency, you are not going to be able to capture them.

Reducing the error

The easiest way is to either reduce your resistance on your divider, or to buffer your signal. When you buffer the signal you will replace the PICs leakage current with your op-amps leakage current which you can get quite low.

This 1uA is a worst case, unless it costs you a large amount to make minor changes to the design, fab your design and test how bad it is for you.

Please let me know if there is anything I can do to make this easier to read.

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  • \$\begingroup\$ Okay, 3% is quite high... is there any way to reduce this? I guess I could reduce the divider resistance... \$\endgroup\$ – Thomas O Oct 22 '10 at 7:00
  • \$\begingroup\$ it is 3% if your smallest reading is 30V. \$\endgroup\$ – Kortuk Oct 22 '10 at 14:31
  • \$\begingroup\$ extra information added. \$\endgroup\$ – Kortuk Oct 22 '10 at 14:35
  • \$\begingroup\$ @Kortuk 100 mV over 1 uA leads to 100 kΩ resistance, but I cannot figure out where that resistance is coming from. Can you clarify that, please? \$\endgroup\$ – elektrodynamik Mar 16 at 9:40
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MCU ADC inputs can experience variable input impedance depending on whether the sample-and-hold cap is connected to the pin or not. It might be worth the trouble to use an op amp to buffer the signal. The op amp would have the added benefit of allowing you to filter out frequencies above Nyquist, which is also good practice.

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  • \$\begingroup\$ Unfortunately I can't spare space for an op-amp. \$\endgroup\$ – Thomas O Oct 20 '10 at 18:36
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    \$\begingroup\$ you can't spare space for a SC70-6 component and you call yourself a noob? \$\endgroup\$ – akohlsmith Oct 22 '10 at 12:37
  • \$\begingroup\$ agreed, one op amp for filtering below the nyqusit rate and setting the gain, and the second optional one for buffering the input. \$\endgroup\$ – smashtastic Oct 22 '10 at 22:02
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One point not yet mentioned is switched capacitance on the input. Many ADCs will connect a capacitor to the input while they take a measurement and then disconnect it sometime later. The initial state of this cap may be the last voltage measured, VSS, or something inconsistent. For accurate measurement, it is necessary that the input either not budge when the capacitance is connected, or that it bounce and recover before the capacitor is disconnected; in practice, this means that either the capacitance on the input must be above a certain value, or else that the RC time formed by the input capacitance and source impedance must be below a certain value.

Suppose, for example, that the switched input capacitance is 10pF, and the acquisition time is 10uS. If the input impedance is 100K, there is no input capacitance other than the capacitance of the ADC, and the difference between the starting cap voltage and the voltage to be measured is R, then the RC time constant will be 1uS (10pF * 100K), so the acquisition time will be 10 RC time constants, and the error will be R/exp(10) (about R/22,000). If R might be the full-scale voltage, then the error will be a problem for 16-bit measurements, but not for 12-bit measurements.

Suppose there were 10pF of capacitance on the board in addition to the 10pF of switched capacitance. In that case, initial error would be cut in half, but the RC time constant would be doubled. Consequently, the error would be R/2/exp(5) (about R/300). Barely good enough for 8-bit measurement.

Increase the capacitance a little more and things get even worse. Push the capacitance to 90pF and the error would be R/10/exp(1) (about R/27). On the other hand, if the cap gets much bigger than that, the error will go back down. With a capacitance of 1000pF, the error would be about R/110; at 10,000pF (0.01uF), it would be about R/1000. At 0.1uF, it would be about R/10,000, and at 1uF, it would be about R/100,000.

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Take a look at page 198 of the datasheet. There's 6-11pF at the pin and 4.4pF on the holding cap.

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  • \$\begingroup\$ Yes but what does this mean to me? Sorry, I'm still a noob. \$\endgroup\$ – Thomas O Oct 20 '10 at 17:27
  • \$\begingroup\$ The input will draw about 500nA (the current source). The capacitors will limit the sample rate. The Chold needs time to charge when it switches to the input pin. \$\endgroup\$ – Robert Oct 20 '10 at 17:42
  • \$\begingroup\$ 500nA would drop 50mV, which is quite high, but not much of my 0-30V full scale range, it would be about 5mV which is fine. Thanks! \$\endgroup\$ – Thomas O Oct 20 '10 at 17:48
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In addition to the good points that supercat has raised in his post, there is a further subtlety to note when you are using an unbuffered voltage divider with an external capacitor.

The charge transfer that happens every time you run through a sequence of ADC readings, when multiplied by a sequence repeat rate, becomes a current. The DC average value of this current is Csamp * deltaV * f, where Csamp is the sampling capacitance (not the external capacitance!), deltaV is the voltage between successive input channels, and f is the sequence repeat frequency (how often you cycle through 1 complete sequence of samples).

When you have an external capacitor to reduce the charge transfer effects and keep from having a long sampling time, it has the negative effect of low-pass-filtering this input current required to charge the sampling capacitor, which will appear as an input-voltage-dependent leakage current that causes an offset voltage across your source impedance.

Just for some sample numbers: your voltage divider (100K || 10K) is about 9K, and if deltaV between channels = 3V, Csamp = 10pF, and f = 10kHz, this will cause a voltage error of 2.7mV, or slightly less than 0.1% of deltaV. Not a lot, but enough to be aware of. You should not be using a 1M || 100K voltage divider with 10kHz sequence repeat rate -- of course, this is fairly fast, and for slower repeat rates, you don't need to worry as much.

I've written about this and other ADC driving issues in a post on my blog.

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  • \$\begingroup\$ Your point about repeated capacitive switching appearing as a continuous current is a good one. In the scenario where I had the most trouble with the capacitive switching behavior my sampling rate was below 1Hz, so the current sourced or sinked by the switched input was a non-issue, but for situations involving continuous data acquisition it's a problem that won't be solved by an input filter cap no matter how big it is. \$\endgroup\$ – supercat Aug 27 '12 at 19:21
  • \$\begingroup\$ BTW, with regard to your blog, another couple approaches to solving the type of problem the other engineer had may be to change the polling sequence to (sample thermister #1), (sample fixed zero-volts signal), (sample thermister #2), (sample fixed zero-volts signal), or else, if the starting point for the cap is always the previous voltage that was read, sample each thermister twice for each sample group, either just using the second value, or perhaps adjusting the second value based upon the other sensor's second reading and the first read value. \$\endgroup\$ – supercat Aug 27 '12 at 19:28

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