I've been playing with a few logic simulators and don't understand why flip-flops are not working. I'm trying to implement a T flip-flop with NAND gates:

enter image description here

All the simulators I've tried give the same result. Either Q or Q' takes the state of the clock rather than toggling on the rising edge, depending on the timing of the internal updates. Given the symmetry of the circuit I'm not that surprised, but wonder how it's meant to work in practice.

Is this even possible, or do these imulators provide flip-flop components because it's not possible to do with basic parts? If so, why and what is missing?


NAND gate circuit compared to a provided T flip-flop (circuitverse.org):

enter image description here

The same in simulator.io (using AND+NOT as there's no NAND):

enter image description here

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    \$\begingroup\$ Where did you find this circuit? It doesn't look like an edge-triggered flip-flop to me. \$\endgroup\$ Commented Jan 3, 2021 at 0:25
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    \$\begingroup\$ This question is getting kinda repetitive now. \$\endgroup\$
    – Mitu Raj
    Commented Jan 3, 2021 at 6:55
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    \$\begingroup\$ Does this answer your question? JK latch, possible Ben Eater error? \$\endgroup\$ Commented Jan 3, 2021 at 7:24
  • \$\begingroup\$ Another point to be noted: A T Flip-Flop with only 2 inputs: T and Clock has no way to get into a known state in simulation. \$\endgroup\$ Commented Jan 3, 2021 at 17:22
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    \$\begingroup\$ flip flops rely on analog and are not purely digital, you need to do a spice sim not a logic sim. which also means expose the transistors. \$\endgroup\$
    – old_timer
    Commented Jan 5, 2021 at 7:18

5 Answers 5


Because from this page, the style that you show only works if the width of the clock pulse is tuned to be long enough for the output stage to react, yet short enough for the thing to not oscillate. A logic simulator that doesn't model propagation time may not be able to cope.

To simulate your circuit, you'd need a circuit simulator that 'understands' propagation delay, or you'd need to simulate your circuit at the transistor level.

That same page shows this circuit for a fully synchronous J-Kflip-flop (just connect J & K together for a T f-f):

enter image description here

You may want to try that in your simulator, see what happens.

  • \$\begingroup\$ The output will be 'X' and remain 'X' \$\endgroup\$ Commented Jan 3, 2021 at 14:29
  • \$\begingroup\$ @ShashankVM Sounds to me like Multisim Live is broken. \$\endgroup\$ Commented Jan 3, 2021 at 15:35
  • \$\begingroup\$ @ElliotAlderson, really? What do you expect to get when you do a 4-state simulation in Verilog? \$\endgroup\$ Commented Jan 3, 2021 at 15:36
  • \$\begingroup\$ @ShashankVM Are you saying that the JK flip-flop shown won't work, or are you saying something else? Why would an asynchronous input be necessary to initialize a storage element? When you use the word "it" in your first comment are you referring to Multisim or to the circuit? \$\endgroup\$ Commented Jan 3, 2021 at 15:38
  • \$\begingroup\$ @ElliotAlderson, I know that a T Flip-Flop built using the JK Flip-Flop shown here won't work in MultiSim Live \$\endgroup\$ Commented Jan 3, 2021 at 15:39

The circuit you show is a gated JK latch, not a flip-flop. It suffers from a flaw: with T high and clock high, the cross-coupled NAND gates form a ring oscillator. This is sometimes called the ‘race-around’ problem. The output never settles until the clock is brought back low.

This circuit is illustrative of how not to make a clocked flop. Otherwise it’s useless. An actual toggle flop will use a pair of latches in two stages, clocked on opposite levels. This is sometimes called an ‘edge-‘master-slave’ flip-flop. The variant using a trio of latches (6 gates total) is called 'edge triggered’. Either way, these don't suffer the 'race around' flaw.

More here: How is the Q and Q' determined the first time in JK flip flop?

And here: JK latch, possible Ben Eater error?

  • \$\begingroup\$ I solved the problem by building a down-edge-triggered flipflop directly out of gates. An edge detector is simply an or or an and gate with a bubble on one of its inputs and both inputs tied to the signal. The homework grader didn't understand the circuit. :( \$\endgroup\$
    – Joshua
    Commented Jan 4, 2021 at 4:42
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    \$\begingroup\$ That’s a 1960s solution, when gates were expensive. It would not be used now. I show an example in the Ben Eater question. \$\endgroup\$ Commented Jan 4, 2021 at 6:12

To implement an edge triggered T Flip-Flop that does not rely on gate delay timing, requires, I believe, a minimum of 6 Nand gates. The circuit below simulates fine in CircuitLab.


simulate this circuit – Schematic created using CircuitLab


Someone has commented that this circuit is not a T flip-flop because the circuit depends upon the clock alone, and does not have separate T and clock inputs.

However, when I google "T flip-flop", the very first hit that comes up for me is this which states:

The T or "toggle" flip-flop changes its output on each clock edge, giving an output which is half the frequency of the signal to the T input.

It is useful for constructing binary counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-flop by tying both of its inputs high.

and which contains the graphic:

enter image description here

I don't claim that this is necessarily an authoritative refutation of the claim that a T flip-flop must have separate T and clock inputs. (There is certainly a lot of misinformation about flip-flops on the interwebs. For example, the OPs circuit, shows up all over the place labeled as a T flip-flop despite the fact that it has problems described in other answers.) However, I am offering the above information as an alternative point of view to that of the commenter.

Edit2: A commenter has asked for a state diagram for the circuit. I will provide this information, but not as a diagram.

There are 4 stable states and 12 states that are transistional between stable states in normal operation.

The stable states are:

State: Vin N1 N2 N3 N4 N5 N6

S1: 0 1 1 0 1 1 0

S2: 1 0 1 0 1 0 1

S3: 0 1 1 1 0 0 1

S4: 1 1 0 1 1 1 0

The transitions go as follows

S1 In\$\uparrow\$ N1\$\downarrow\$ N6\$\uparrow\$ N5\$\downarrow\$ S2

S2 In\$\downarrow\$ N1\$\uparrow\$ N4\$\downarrow\$ N3\$\uparrow\$ S3

S3 In\$\uparrow\$ N2\$\downarrow\$ N5\$\uparrow\$ N6\$\downarrow\$ N4\$\uparrow\$ S4

S4 In\$\downarrow\$ N2\$\uparrow\$ N3\$\downarrow\$ S1

  • \$\begingroup\$ This circuit toggles on the rising edge of the clock, which is what a T Flip-Flop does. You can add bells and whistles like a set or reset inputs, a gate for toggling, etc, but I don't think they are necessary for a T Flip-Flop. Maybe I am mistaken. But then again, I see a lot of latches being passed off as T Flip-Flops on the interwebs. The OPs circuit is everywhere, (just google T flip flop, and look at the images) and it doesn't work with discrete components. It might work in an IC where propagation delays are carefully matched / controlled. So who knows what is really a T flip flop? \$\endgroup\$ Commented Jan 3, 2021 at 6:44
  • \$\begingroup\$ @ShashankVM I have responded with an edit to my answer. \$\endgroup\$ Commented Jan 3, 2021 at 14:57
  • \$\begingroup\$ If you tie J and K high, then there is only one input that toggles the output, which in that case is called "clk". Whether the toggle input is called "clk" or "T" is just a matter of labelling. There is no contradiction in what they are saying. \$\endgroup\$ Commented Jan 3, 2021 at 15:11
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    \$\begingroup\$ You are arguing about the usage of a word. Whether you call my circuit a T flip-flop or not, the point remains that a T flip-flop requires either a minimum of 6 nand gates, or carefully controlled timing. The OP asked why a circuit found all over the internet doesn't simulate as advertised. I offered a circuit that does simulate correctly, but requires more nand gates than the OP used. Not going to argue the point any more whether my circuit is or is not a T flip-flop. We both know what it does, and unlike the circuit of the OP, it simulates correctly (at least on CircuitLab). \$\endgroup\$ Commented Jan 3, 2021 at 16:31
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    \$\begingroup\$ Not sure from where you got that definition from Google, cz what you have presented above is a Frequency/2 divider as "T Flip-Flop". Wikipedia clearly says what is a T Flip-Flop . en.m.wikipedia.org/wiki/Flip-flop_(electronics) \$\endgroup\$
    – Mitu Raj
    Commented Jan 4, 2021 at 8:43

Another issue you might (but should) run into is this: How is the Q and Q' determined the first time in JK flip flop?.

This is especially true for a T Flip-Flop.

For a T Flip-Flop with only 2 inputs, T and Clock, there is no way for the output to get into a known state in a simulation that supports 'X'.

A good simulator will shown an 'X' on both outputs, which shows that the value is unknown.

As I have mentioned in my answer, one can use synchronous or asynchronous inputs to set the output to a known state.

For reference, I've built a T Flip-Flop with asynchronous inputs using a Master Slave JK Flip-Flop, which you can simulate in your browser:

T flip-flop simulate this circuit - Schematic created using MultisimLive


The circuit in the original question contains 1 or more hazards or race conditions. As such, the circuit will only work properly if the delays within the circuit are properly controlled.

An asynchronous finite state machine with hazards (or race conditions) will, in general, work properly only if delays within the circuit are properly controlled. An asynchronous finite state machine without hazards (or race conditions) or with hazards which are "covered" (and hence not active) will perform properly if there is at any time only one signal which is changing, and which does not receive new inputs until the circuit has reached a stable state.

Such asynchronous finite state machines may be implemented in a number of ways, but one way to do so is with a sum-of-products combinatorial circuit with some of the outputs fed back as inputs.

In this answer, such a circuit will be shown. However, it is probably unfamiliar to many, and is certainly less familiar than other implementations of T flip-flops, such as the master-slave implementation, or the 6 nand gate implementation shown in another answer.

We start with an asynchronous finite state machine that we wish to implement:

enter image description here

The flow table for this state machine is given as:

enter image description here

We can assign variables and values to the states to give:

enter image description here

with the excitation table

enter image description here

The Karnaugh maps for Q, Y and Z are given as follows

enter image description here

enter image description here

enter image description here

If we were attempting to find the minimal implementation of a boolean function, we would calculate a minimal sum of prime implicants that cover the function under consideration. However, such a procedure would allow our implementation to have static 1 hazards. To avoid static 1 hazards, we use extra prime implicants (in this case all of the prime implicants). This gives our combinatorial functions

\$Q = z\$

\$Y = x'z + xy + yz\$

\$Z = x'z + xy' + y'z\$

Finally, implementing this circuit as a sum of products with feedback:


simulate this circuit – Schematic created using CircuitLab

enter image description here enter image description here


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