I'm reverse engineering a laser printer (Laserjet 1320) and I need to infer some things about the memory bus. The full schematic I've made while reversing is here (in pdf) on Drive. I'm not all that familiar with embedded hardware memory mapping and this part confuses me:
The processor is a Freescale ColdFire-based device (in particular, with a ColdFire v2 core) but the particulars are proprietary. Regardless, ColdFire is basically M68k so I would assume the processor address bus is either 24 bits or full 32-bit. The program is stored in mask ROM U8, connected to the 14-bit address bus (A0:A13). Then, address bits A14:A20 are connected to D-latch U5, loaded loaded by A4:A10.
Here's the datasheet for the mask ROM, and the datasheet for the D latch. When U8 is disabled (nCE HIGH) the latch is transparent; then U8 is enabled (nCE LOW) and the latch latches. What I'm wondering is, how is this implemented on the processor side? First, a bit must be set HIGH, then bits A4:A10 are set, then the pin is set LOW, and pins A0:A13 are set. But how does the processor actually access these addresses when they're provided? Does it require two clock cycles when changing the significant bits, and if so, is this a processor issue or an external hardware issue?