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The image shows a buffer register as part of an SPI module

Why exactly is a buffer connected to the FIFO registers?

enter image description here

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  • \$\begingroup\$ Presumably it is a transceiver, that is two back to back tri states? \$\endgroup\$
    – copper.hat
    Jan 4 '21 at 7:27
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It is not a buffer in a way you might think about a buffer.

The SPIxBUF is the name for a IO special function register address that is used to write/read the data to/from FIFOs.

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  • \$\begingroup\$ So essentially itds a memory controller? \$\endgroup\$
    – Yogi Bear
    Jan 4 '21 at 8:32
  • \$\begingroup\$ What does it actually look like? \$\endgroup\$
    – Yogi Bear
    Jan 4 '21 at 8:32
  • \$\begingroup\$ The actual implementation is irrelevant. It is a bunch of logic gates that can be abstracted as per the block diagram to provide you a high level understanding how the SPI peripheral works - i.e. you use SPIxBUF name in your code to read and write data. \$\endgroup\$
    – Justme
    Jan 4 '21 at 8:56
  • \$\begingroup\$ I believe the implementation is not irrelevant, the diagram provides high level details of functionality. Without the implementation you would essentially have to force relations, there may also be further requirements not listed in the high level representaiton which can be derived form the implementaiton itself \$\endgroup\$
    – Yogi Bear
    Jan 4 '21 at 8:59
  • \$\begingroup\$ So an example implementation is always best for providing understanding \$\endgroup\$
    – Yogi Bear
    Jan 4 '21 at 9:00

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