# Does this interrupt improve performance even with while loop in ISR?

Note: I am a beginner :) MCU: Atmega328p

Which program below burdens the CPU the least? Would it be a significant difference?

Objective: to make a more "efficient" serial monitor by reducing the CPU burden.

Both programs send the int num = 65534 to my PC where I can see value coming in repeatedly through a serial monitor. Program 1 uses a empty data register interrupt and program 2 does not use any interrupts.

Considering I am still using while (( UCSR0A & (1<<UDRE0)) == 0){} in uarttrasnmitinteger function within the ISR in program 1, does program 1 reduce the "workload" of the CPU compared to not using this interrupt such as in program 2 (see below)?

Program 1:

char snum[20];
int num = 65534;

int main (void) {
uarttransmitenable();
sei();
while (1) {
//no code here
}
}

ISR(USART_UDRE_vect) {
uarttrasnmitinteger(num, snum);
}

void uarttransmitenable(void) {
UBRR0H = (BRC >> 8);
UBRR0L = BRC;

UCSR0B = (1<<TXEN0)| (1<<RXEN0) | (1<<UDRIE0);
UCSR0C = (1<<UCSZ01) | (1<<UCSZ00);
}

void uarttrasnmitinteger(unsigned int num, char* snum) {
utoa(num, snum, 10);
unsigned int i;
for (i=0; i<strlen(snum); i++) {
while ((UCSR0A & (1 << UDRE0)) == 0) {}
UDR0 = (char)snum[i];
}
}


Program 2:

char snum[20];
int num = 65534;

int main (void) {
uarttransmitenable();
while (1) {
uarttrasnmitinteger(num, snum); // same function used in program 1
}
}

void uarttransmitenable(void) {
UBRR0H = (BRC >> 8);
UBRR0L = BRC;

UCSR0B = (1 << TXEN0)| (1 << RXEN0);
UCSR0C = (1 << UCSZ01) | (1 << UCSZ00);
}

• Is this the only operation you will do or there are other operations and process in your project?
– CNA
Jan 5 at 3:31
• A while loop in an ISR is severely unwise, basically missing the whole point of an ISR Jan 5 at 5:06

Branching to the interrupt, saving registers, restoring registers, and then returning from the interrupt all take clock cycles. If the only thing you are doing is transmitting this serial data, then not having the interrupt is going to use less clock cycles overall.