0
\$\begingroup\$

Point 2 of page 16 in this document (image shown below) states that:

The contents of SPIxTXB are moved to the shift register SPIxSR

Exactly how is it moved, is it moved serially or in parallel?

I don't understand why they don't provide these implementation details... Could someone clear this up for me please who has implemented SPI before or has documentations showing the actual electronic implementation.

enter image description here

Source: https://pages.hmc.edu/jspjut/class/f2013/e155/docs/Section%2023%20Serial%20Peripheral%20Interface%20(SPI).pdf

enter image description here

\$\endgroup\$
6
  • \$\begingroup\$ It could be serial OR parallel - we don’t really know but I suggest it would be parallel as doing it serially would be double handling that would add little value. \$\endgroup\$
    – Kartman
    Commented Jan 5, 2021 at 11:51
  • 1
    \$\begingroup\$ Figure 23-5: in your datasheet. I'm fairly certain it is shift registers, so the register content will be moved sequentially into the FIFO buffer "stack" at X clock cycles. There might be some shadow registers and stuff going on under the hood. \$\endgroup\$
    – Sorenp
    Commented Jan 5, 2021 at 11:52
  • 1
    \$\begingroup\$ This is third similar question about this subject? Surely the CPU write to SPIxBUF would be as fast as possible so it is parallel loaded to FIFO. How the FIFO operates with SPIxSR is another thing, but as it seems user can skip FIFO so most likely the interface is such that for the SPIxSR it is irrelevant if the data is loaded directly by CPU write or by FIFO. The reason these details are not given because it is irrelevant, somebody writes high level HDL to describe the peripheral and a synthesis tool instantiates it. It might be that even the manufacturer does not know the exact details. \$\endgroup\$
    – Justme
    Commented Jan 5, 2021 at 11:52
  • \$\begingroup\$ Also that is your opinion @Justme, there could easily be other conditions which mitigate the parallel transfer. Thats why im asking for an expert who has implemented before in hardwasre not some hobbyhist with opinion based upon limited knowledge \$\endgroup\$
    – Yogi Bear
    Commented Jan 5, 2021 at 11:55
  • \$\begingroup\$ If the chip is using register renaming there might not be a physical transfer at all (just a swap of the two registers' roles). \$\endgroup\$ Commented Jan 5, 2021 at 13:26

1 Answer 1

4
\$\begingroup\$

The implementation details aren't provided because they are not visible to the user and thus do not matter to the user. To hazard a guess, the transfer is probably done in parallel.

As each bit is shifted out of the shift register and transmitted a bit is read and pushed onto the opposite end of the register. Once 8, 16, or 32 bits have been written and read the user is notified and another word of data can be written/read.

\$\endgroup\$
1
  • \$\begingroup\$ I haven't used this chip but I would agree with this answer. You read/write the transfer register when it is ready, i.e. when 8/16/etc bits have been exchanged. \$\endgroup\$
    – Pete W
    Commented Jan 5, 2021 at 12:57

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.