After getting some helpful critiques from my original post;

Critique my SMPS buck design

I worked on my design and made a few major changes.

  • L1: 3.3uH 2A inductor
  • C1: 10uF 25V ceramic cap
  • C2: 0.01uF 16V ceramic cap
  • C3: 22uF 6.3V ceramic cap
  • D1: RB160M (input protection)
  • D2: RB160M (catch diode)
  • D3: BAV99W (dual diode)
  • R1: 10k 0.1%
  • R2: 31.6k 0.1%
  • R3: 56R
  • LED1: blue LED, 2.85V, 5mA
  • U1: LM2734Z (3 MHz variant), SOT-23-6

I have added some copper around the pins in an effort to remove heat from the IC. The only thing I'm presently worried about is if the trace for the feedback voltage is too long.

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Yellow is the critical current flow out, not sure where it goes from the output cap, C3.

Pink is the ground return, kinda sorta, theres a few critical loops in a circuit like this, some follow the path of least resistance, some follow the path of least impedance (follow their supply trace).

Keep in mind your goal is to minimize the size of this loop and minimize the resistance between yellow/pink at high frequency, (minimize impedance to ground).

Lets just quote the datasheet since it covers all of this:

"When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most impor- tant consideration when completing the layout is the close coupling of the GND connections of the CIN capacitor and the catch diode D1. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. "

C1 and D2 in this case. C1 has a really, really, long path to ground for a power supply decoupling cap. Its also on the other side of the circuit from D2's ground. When your talking about high frequency PCB design when it says "tightly coupled" that doesn't mean just both tied to a ground plane. It means both ground pins are right next to each other, with a surface polygon pour connecting them and multiple via's to a ground plane right next to the pads.

Incidentally aren't your diode silkscreen's backwards?

"Next in importance is the location of the GND con- nection of the COUT capacitor, which should be near the GND connections of CIN and D1."

C3 is the output cap and its ground is roughly as far away from the other 2 as you can get.

"The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R2 placed as close as possible to the GND of the IC. The VOUT trace to R1 should be routed away from the inductor and any other traces that are switching."

Think your ok with this one, your probably better off running the trace from C3 further away from the inductor but its probably ok.

"High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the de- signer must make this trade-off. Radiated noise can be de- creased by choosing a shielded inductor."

If were you i'd just use polygon pours for most of these connections, just make sure you have appropriate filtering in place and a shielded inductor.

"The remaining components should also be placed as close as possible to the IC. Please see Application Note AN-1229 for further considerations and the LM2734 demo board as an example of a four-layer layout."

If using 4 layer why not reference that app note? pretty much covers using a big ol' ground pour for the critical ground return and a pour for the SW output.

  • \$\begingroup\$ Thanks for your suggestions! I noticed the diode silkscreens were the wrong way around too. I think I will start again. I am trying to use 2-layer for this version to cut down costs. \$\endgroup\$
    – Thomas O
    Oct 21 '10 at 7:01
  • \$\begingroup\$ Think carefully about going to 2-layer. The layout will be far superior not only electrically but thermally if you go with 4-layer and use planes to minimize loop sizes. \$\endgroup\$ Oct 21 '10 at 16:46
  • \$\begingroup\$ Yeah, but it's twice the cost to prototype 4-layer, I can't afford that at the moment. \$\endgroup\$
    – Thomas O
    Oct 21 '10 at 18:03
  • \$\begingroup\$ I have had a few students make buck, boost, and book-boost circuits on only 2 layers and got it to work just fine. I would highly consider using a ground plane on the bottom with many vias connecting to your ground on the top. Pretty much, instead of looking for a way to route ground on the top, just place a via any where you need ground. \$\endgroup\$
    – Kellenjb
    Oct 22 '10 at 5:54
  • \$\begingroup\$ I may be misreading it, but the design seems to have a ground plane. \$\endgroup\$
    – Kortuk
    Oct 22 '10 at 20:42

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