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So below is a receiver diagram taken from: https://people.ece.cornell.edu/land/courses/ece4760/PIC32/Microchip_stuff/Ref_Manual/section_21_UART.pdf

I can see that there is a clock "BAUD rate clock from baud rate generator" It enters into the divider, is this the divided clock? Or is it the system clock which is divided by the control signal BCLKx?

Also what is the component: Start bit detect, parity check, stop bit detect, shift clock generator, wake logic

Thanks

enter image description here

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  • \$\begingroup\$ Documentation for the Baud Rate Generator should be able to answer that. \$\endgroup\$ Jan 7, 2021 at 16:00
  • \$\begingroup\$ Yogi are you done with this question now or do you still need clarification on some point or other? \$\endgroup\$
    – Andy aka
    Feb 1, 2021 at 16:02

2 Answers 2

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The clock coming from the generator would be (typically) 16 times the baud rate, to allow for oversampling of input data by 16x. So each bit on bus is 16 clocks.

Start bit detection logic looks for incoming start bit to start the reception of a data frame. It typically checks that too short glitches is not considered as start of frame, while long enough logic low is considered as a start of frame, and the reception of data bits is aligned to the middle of data bits.

So as per above, the generated shift clock would load in data bits from middle of each bit.

Parity checking would make sure that when parity is used, a parity bit that matches the data and parity settings is received, otherwise a parity error is signaled along with the received byte.

Stop bit detection would check if the expected stop bit of a data frame is idle, otherwise there is something wrong with the reception and the received byte is signaled with framing error.

Wake logic can wake up MCU from sleep mode when there is a frame being received.

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I can see that there is a clock "BAUD rate clock from baud rate generator" It enters into the divider, is this the divided clock?

Let's be accurate: it says Baud clock. It doesn't say BAUD rate clock

So, if you search (CTRL-F) the document for Baud clock you find this: -

enter image description here

So no, it is not the divided clock because normally it is 16x the baud rate. It feeds into a divider anyway so it would be pretty useless if it was toggling at the baud rate.

Also what is the component: Start bit detect, parity check, stop bit detect, shift clock generator, wake logic

They are event flags for use by some other unspecified logic.

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