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I cannot understand how this current limiting circuit works.
Image source: UNLV Physics Department, Bill O'Donnell, Current Limiter Circuit
Here is where I get confused:
When Q2 is turned on, the voltage at the base of Q1 becomes close to 0 and Q1 stops conducting current. Therefore VR1 should be 0, which will turn off Q2 and turn on Q1. What am I missing here? If we put an emitter resistor for Q2, shouldn't that solve my issue?
It balances around the voltage drop across R1.
Q2 doesn't just suddenly turn fully on. As current through the load increases, the voltage drop across R1 increases...once it gets high enough (around 0.7 V) Q2 STARTS to conduct. At low enough currents, this transistor is just barely conducting current.
Once Q2 starts conducting it starts reducing the base voltage on Q1.
It stays in equilibrium. As the current goes down, so does the R1 voltage drop, so Q2 conducts less, so Q1 lets more current through.
When Q2 is turned on, the voltage at the base of Q1 becomes close to 0 and Q1 stops conducting current. Therefore VR1 should be 0, which will turn off Q2 and turn on Q1. What am I missing here?
You are analysing it like a series of bang-bang events where there is no halfway house between events. If the circuit had a time lag, pretty much that would happen however...
Negative feedback occurs that causes Q2 to start conducting (very slightly turn on) and, this microscopically reduces that voltage at the base of Q1. This slight reduction in voltage causes Q1 to slightly conduct less which in turn means the base voltage to Q2 is microscopically smaller. This in turn means current regulation. It's a linear circuit with negative feedback when the load current tips too far.
When VR1 becomes >0.6V Q2 starts conducting which lowers the base voltage of Q1 and therefore Ib1 is decreased which lowers VR1 and current from Q2. But there must be an emmiter resistor for Q2 which will not let the voltage base of Q1 to become less than the needed voltage for Q1 to conduct.
It is a linear amplifier that becomes nonlinear with a series R that depends on the gain of the driver and current it draws to limit the current in the output as it produces 0.65V across Re the driver collector produces a few mA which is then amplified by Q2 to regulate the current. Above this the CC an apparent ESR that depends on the re of the output device or 1/gm divided by hFE of the driver. This can be made flatter using a higher gain driver, or even better a differential amplifier as used internally in LDO’s configurations relative to Vadj.
