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I am attempting to simply crop or resize the images as they are streamed to the frame grabber using the FPGA onboard this Euresys Coaxlink Quad CXP-12 frame grabber. The frame grabber has an XCKU035 FPGA and comes with this Custom Logic design kit that allows me to upload my own FPGA bitstream to the frame grabber to perform any image processing needed.

I'm new to HLS and FPGAs and am not exactly sure where to start on this. I read into the Xilinx xfOpenCV library that has a resize function but I have no idea if it would work in my case or how to implement it yet. Does anyone know where I should start on this?

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  • \$\begingroup\$ This seems to be all about how to use existing IP rather than actual design, I'm not sure it's a good fit here : Xilinx own forums are likely to be more useful. \$\endgroup\$ Jan 8 at 15:22
  • \$\begingroup\$ Where to start would probably be: get a test program to run on the FPGA. If it's like every other FPGA devkit, it probably has an LED you can blink. You will need to find a schematic to see which things are connected to which pins. \$\endgroup\$
    – user253751
    Jan 8 at 23:59

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