0
\$\begingroup\$

I have a bitstream of about 10-20 MHz coming out of an FPGA, that is obtained by Delta Sigma modulation. This bitstream is expectedly very jittery and can not be passed directly through an analog filter to restore the desired waveform.

The standard approach seems to be passing the bitstream through a D flip flop that is clocked from a synchronous low jitter clock. There are numerous PLL based clocking chips for a few $ that offer even below 100 fs RMS jitter in e.g. 12kHz-20Mhz. Achieving such low jitter in the bitstream would be wonderful.

But I am concerned that the flip flop itself will add much more random jitter. Googling for fast flipflops, I found e.g. this LVDS Flipflop NB7V52M from OnSemi. It states an RMS jitter spec of almost 1 ps, which is much worse than what some PLL Clocks offer. I suppose fast CMOS based Flipflops like the SN74AUC1G79 from TI would be even worse. On the other hand, ECL flipflops like the MAX9381 have jitter figures that are at least close (albeit still higher) higher than that of PLL Clock sources such as the Si5380A.

So Question 1: Is it possible to achieve well below 1 ps RMS jitter in the bitstream output using Flipflops? Or is it possible in another way?

Question 2: If it turns out that reclocking using flipflops does not yield ultra low jitter, then what are such clocks even useful for ? Aren't they always fed into some logic sooner or later to do actual stuff, at which point their impressively low jitter figure gets deteriorated by the actual device?

\$\endgroup\$

2 Answers 2

1
\$\begingroup\$

Assuming you have a suitable low noise clock source to start with, there are ways to improve a basic flip-flop when retiming your synchronous data stream.

Obviously, read the specs, which you are already doing, and choose the lowest jitter available. These tend to be the higher power, higher voltage swing devices, that need more current available to charge their output and internal nodes.

Modern fast devices don't necessarily give you the best jitter. If they have been designed for speed using small internal geometries and small swings, they could end up quite noisy.

Don't overlook plain old 10K and 100K ECL. They are fairly high power.

Some long time ago doing a phase noise investigation, I built a few gates of ECL logic from discrete BFR90 devices, which allowed me to choose the bias currents needed to charge the huge nodal capacitances. I was unable to measure their noise floor with the equipment I had to hand.

If you have a good device, you can make it 3dB better by putting two in parallel, 6dB for four in parallel and so on. You can't simply take an octal flip-flop and parallel the outputs for 9dB improvement if the input clock path is shared between all of the output bits, you would need to take 8 individual packages for that. This improvement gets power, space and cost hungry real fast, so it's the last thing you do once you've found the best single device.

\$\endgroup\$
2
  • \$\begingroup\$ Thanks for the insight. So it looks like my basic assumption was correct, that the Flipflop Jitter will dominate in the cases I mentioned. Going to high power stuff like ECL therefore sure looks like the correct route. Out of curiosity, how do PLL based Jitter Cleaners actually achieve their low output RMS jitter? What kind of output stage are they using ? They don't use that much current usually.. \$\endgroup\$
    – tobalt
    Jan 8, 2021 at 11:21
  • 1
    \$\begingroup\$ @tobalt If a circuit is designed from the outset to be low jitter, then that part of the circuit can be optimised with large area devices, and the rest of the circuit designed for high speed/low power. If you take random logic devices however, there's no usch optimisation going on. Some two decades ago, I designed a low noise programmable 1.5 GHz divider IC, floor noise -160dBc, the low noise path was just one T-flop which together with its input and output buffers took up half the chip area, the programmable control counters took up the other half. \$\endgroup\$
    – Neil_UK
    Jan 11, 2021 at 11:37
2
\$\begingroup\$

OK, the question is a bit old, but...

When I designed my DAC I had a look at the jitter of various logic gates. I don't remember the numbers, but basically standard stuff like 74HC don't add much.

However there is a big difference between a gate/flop buffering/dividing a clock, which is a periodic signal, and a gate/flop processing a random bitstream, which is not periodic.

The output jitter of your gate/flop depends on several things:

Internal transistor noise, which you can't change (smaller faster transistors have more noise than big slow FETs though).

Input threshold voltage on clock input, which is basically VCC/2. If the clock has a slew rate of S V/ns, say 1V/ns for a 3ns rise time 3V3 signal, and the power supply has noise voltage V, the input threshold has noise V/2, which means this generates jitter V/(2S). When the threshold moves, due to clock slew rate, it will catch the transition earlier or later. This also happens inside the chip between the various stages.

This means one of the most important things is that the power supply and ground voltages inside your chip must be stable and repeatable. Otherwise you get threshold voltage modulation, and therefore jitter.

If S=1V/ns and noise V=20mV, then jitter is 10ps. With realistic values this always makes the gate/flop's intrinsic jitter quite meaningless as threshold modulation will dominate.

This is not a problem if the gate is processing a clock, because a clock is periodic. Just use a reasonably low noise power supply (not the VCC from your FPGA!).

However if the gate is processing a random bitstream, it's game over. Its power supply current will depend on the bits, it will output current dependent on the bits, so the power supply will wiggle according to the interaction of that with the LDO's transient response, the caps, etc.

In addition, you're only considering the jitter, but the output high level of your gate is equal to its power supply. If there is ripple voltage there, your output signal will be multiplied by it. On the FFT if you got 100Hz ripple there it looks like jitter, you get two peaks spaced 100Hz away from your main signal. So you can test at different frequencies, because if the peaks are due to jitter their amplitude will increase with frequency, but if your signal is being modulated by power supply ripple, then it won't.

So the trick is to make the power supply current of the gate constant. This means going differential. This is why all high performance sigma delta modulators have differential outputs, and they draw constant current on whatever rail is used as voltage reference. For example ES9018 does, unless you use only one polarity and don't use a differential output circuit, in which case power supply current (and analog reference voltage) is modulated by the output signal value, and you get a pretty big increase in THD, and then every component in the AVCC rail becomes part of your signal chain, and you hear the transient response of your regulator, and audiophiles write 500 page topics about the best choice of gold plated caps. Whereas if you use both polarities on the differential output, it draws constant current as intended by the designer, so you just need good HF decoupling and a stable ripple free power supply.

You don't have to use LVDS, you can use LVCMOS, but your FPGA should output two complimentary signals, going to two flops in the same 74HC74 chip, and the outputs should be loaded the same, for example with a RC filter followed by a differential input opamp circuit. Basically, do anything you want, as long as the power supply current, output current, and ground current of your gate DO NOT depend on the random bits on the bitstream.

The power supply should be free of ringing. It will spike at each transition, but it should settle cleanly back to nominal voltage after each transition. If it is still ringing when the next transition comes, who knows what the threshold voltage will be. Easy to check with scope. This means one local MLCC, not two, check ferrite beads for ringing, tight layout, etc.

You can then feed it with a low-noise LDO, which will meet its low noise spec. They only do that on constant current loads, otherwise refer to the transient response graph in the datasheet.

Only after this is fixed, you can consider the intrinsic jitter of the gate.

Note that this differential scheme comes with a big gotcha. If you measure noise on the output, with zero digital input, it will be very low because noise appears as common mode on the output and the output differential opamp rejects it. However if you make it output say a digital value of half-scale or full-scale DC, then the output will be equal to that proportion of the flop's power supply voltage, and then the noise and ripple on the flop's VCC will appear in the output and be measurable. So this scheme results in noise modulation, where the output contains the flop's VCC noise multiplied by the signal. This means all noise measurements of commercial DACs, which are done with zero output signal, are mostly useless.

If the flops for both channels use the same power supply, a good way to check performance is to have one channel output digital DC, FFT the output, while the other channel is playing a sine. The measured channel should not contain harmonics of the sine played on the other channel.

\$\endgroup\$
6
  • \$\begingroup\$ Here is a lot of good info about the "grand scheme" of low jitter bitstream handling (and I will have to read it a few more times 😉). I am doing most of the things you suggest, but especially the differential handling is something I have neglected in the past. But one thing that you treated a bit shortly is the thing about the internal transistors. Neil already pointed out the advantage of big hungry transistors. You write that "big, slow FETs" are better. Did you mean "big, fast" ? \$\endgroup\$
    – tobalt
    Jan 7 at 9:38
  • 1
    \$\begingroup\$ I can't give figures for specific gates, but you can measure it: feed your clock to two identical flops under test to divide by two. Run one of the outputs through a delay line, like a bit of coax. Run the two divided clocks through an AND gate, and lowpass filter. This outputs a voltage that is proportional to the jitter added by the whole circuit. It will ignore phase noise in the clock, too. \$\endgroup\$
    – bobflux
    Jan 7 at 10:13
  • \$\begingroup\$ Hmm good idea. I probably wouldn't use a gate at the end for fear of its own jitter, but directly use the analog scope method (overlay and trigger on one of them, detect the smearing) \$\endgroup\$
    – tobalt
    Jan 7 at 10:21
  • \$\begingroup\$ It's not really possible to use a scope for that, unless it's a $$$$$ GHz scope with very low specified jitter \$\endgroup\$
    – bobflux
    Jan 7 at 11:21
  • \$\begingroup\$ Ok, I see. Such stuff might be actually around collecting dust in a cabinet.. You never know ;) $$$$ Btw, you found out how to make line breaks in comments, lol. \$\endgroup\$
    – tobalt
    Jan 7 at 11:24

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.