I have a question about the 'correct' way to use test benches to test VHDL components in Vivado.

To give you an idea of my task, I have a source file called Top_Level which is going to be the highest level where all other components are created from.

So I have simple register 32-bit register that is created with structural VHDL in the Top_Level file and is made up of the following hierarchy:

Top_Level => 32_bit_Register => 1_bit_Register

Signals are declared in the Top_Level file and are passed down and back through all the components, so my Top_Level file has no inputs or outputs in it's entity.

Now when I go to create a test bench called Top_Level_TB for the Top_Level file I have a problem as I can't port map my Top_Level signals to my Top_Level_TB file as they are not in the entity.

How should I get around this or is this something I shouldn't do? Relatively new to VHDL.


  • 4
    \$\begingroup\$ How will you use your circuit? Doesn't it need inputs and outputs to do anything useful? \$\endgroup\$
    – Justin
    Jan 8, 2021 at 20:47
  • \$\begingroup\$ @Justin After a while my circuit will have inputs and outputs but this is the first component I am building in the design and want to test it before moving on. Even if I used the inputs now, there is more complex gating to control the register I am testing, so using the inputs are no help really \$\endgroup\$
    – David777
    Jan 8, 2021 at 21:05

1 Answer 1


It sounds like you're trying to test the 32_bit_Register, not the rest of the circuitry in Top_Level.

So don't put a Top_Level entity in your testbench. Put a 32_bit_Register entity in your test bench. After all, isn't that the thing you're trying to test?

  • \$\begingroup\$ Yeah, you are exactly right. This now works. Thank you so much for your help! \$\endgroup\$
    – David777
    Jan 8, 2021 at 23:24

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