I have a question about the 'correct' way to use test benches to test VHDL components in Vivado.
To give you an idea of my task, I have a source file called Top_Level which is going to be the highest level where all other components are created from.
So I have simple register 32-bit register that is created with structural VHDL in the Top_Level file and is made up of the following hierarchy:
Top_Level => 32_bit_Register => 1_bit_Register
Signals are declared in the Top_Level file and are passed down and back through all the components, so my Top_Level file has no inputs or outputs in it's entity.
Now when I go to create a test bench called Top_Level_TB for the Top_Level file I have a problem as I can't port map my Top_Level signals to my Top_Level_TB file as they are not in the entity.
How should I get around this or is this something I shouldn't do? Relatively new to VHDL.