# cmos impedance calculations

I posted a question about a week ago about impedance and have a follow up if you will indulge me.

I'm comparing input and output impedance from TTL and CMOS ICs, specifically 7401 and 4011 NAND gate ICs.

I know that the frequency plays a part but generally I am led to believe that Vcc-Voh/Ioh gives me the high logic output impedance and Vcc-Vol/Iol gives me the low logic output impedance. Right?

For the 4011, the datasheet gives a min Voh of 4.95 at Vcc 5V. So 5-4.95/Ioh(0.88) = 0.05/0.00088 = 56 ohms. Sounds about right. Right?

For the low logic, Vol is max 0.05V @ Vcc 5V. so 5-0.05/Iol(0.88) = 4.95/0.00088 = 5625 ohms. From my internet research, the output impedance from CMOS ICs is low in either logic state so the value of 5625 can't be right. Right?

Also taking the input impedance I'm using Vcc-Vih/Iin and Vcc-Vil/Iin which gives me a high logic impedance of 13Mohm and 36Mohm @Vcc15V (15V as that's all that's provided for Iin) Is this about right? I can't help but think that I should be doing something with Vo as it's specified in the conditions for Vih and Vil.

Datasheet attached If you've read this far perhaps you'll do me another solid. Why does the output impedance matter? I understand that the high input impedance is important for driving other logic gates but what about the low output impedance?

Thank you so much. Appreciate the help I receive here

• The term impedance suggests a fully linear system. Extrapolating your results to the full range between GND and +Vdd would be very wrong. The term incremental impedance is more correct. Perhaps useful for considering noise-immunity while a logic state is statically "high" or statically "low". Jan 9 at 14:19

For logic devices, frequency does not really play a part in impedance calculations; such effects happen at frequencies where the device would not longer be able to generate a proper (square wave) logic signal at the output. Impedance calculations are really DC resistance calculations.

Your output impedance calculations are wrong because the specified VOL and VOH values have an extremely small output current (< 1 µA) as test condition. Use the IOL/IOH entries, and the VO test conditions in those lines.

To compute the input impedance, you also have to take values from the same line, i.e., VIN is either 0 V or 15 V.

The output impedance matters because it specifies how large of a load you can connect directly to the output. Also, a stronger output takes less time to (dis)charge a capacitance, which means that it can more quickly switch between voltage levels.

The Vol/Voh are somewhat artificial in that these are the DC voltage levels. You might be better off looking at the transition between the Vih/Vil levels, i.e. the swing required for the output to appear as a high/low level at whatever input the signal is driving. It’s quite possible that the impedance is significantly lower in this middle range than it is near the extremes. The situation is further complicated by the fact that the transition at the output is not instantaneous, so the loading that’s applied is not the only limiting factor.

Low output impedance is desirable because it generally results in higher switching speeds, particularly where the load is somewhat capacitive (such as a CMOS input). At very high speeds, however, impedance matching of the output, load and transmission line becomes increasingly important since reflections of the signal start to become problematic.

Your output impedance calcs don't look right. Iol is 0.4V @ 880uA. R = V/I = 0.4/880e-6 = 455 Ohms Ioh is the same. 4000 series CMOS did not have strong output drive.