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I'm designing a traffic light using two BCD counters and a JK flip flop. The simulation works perfectly on Proteus, but not in hardware (PCB). The traffic light is required to count from 40 to 0 in some color, and from 20 to 0 in the other color, and repeats again and again.

Here is my simulation:

enter image description here

What happens in hardware is, sometimes the JK flip flop doesn't toggle when the counter resets.

In simulation, when both counters reach zero, the TCD will become zero. Hence, the JK flip flop will receive a falling edge and toggles, and also the counters will reset to either 20 or 40 depending on the flip flop state.

I'm not sure what makes this doesn't work well on hardware. I verified that my connections matches what in simulation. I suspect there is some timing issue that Proteus doesn't consider.

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  • \$\begingroup\$ Where are the decoupling capacitors? What is your power supply? Tip: turn off the grid before taking screengrabs to make the text more legible. \$\endgroup\$
    – Transistor
    Jan 9, 2021 at 11:12
  • \$\begingroup\$ I haven't yet tried adding decoupling capacitors as the clock that goes to the counters is very stable (i.e. the counter doesn't skip any numbers). Do I still need decoupling capacitors? and on which IC? 74HC73? I take my power supply from an Arduino board (VCC and GND pins) \$\endgroup\$
    – Youssef13
    Jan 9, 2021 at 11:18
  • \$\begingroup\$ please provide a schematic diagram of the failing circuit ... the proteus circuit does not show the actual clock source \$\endgroup\$
    – jsotola
    Jan 9, 2021 at 11:22
  • \$\begingroup\$ @jsotola The clock source is a typical timer 555 circuit \$\endgroup\$
    – Youssef13
    Jan 9, 2021 at 11:22
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    \$\begingroup\$ It appears that you are relying on the timing of the 74HC32 and 75HC192s to provide a valid clock pulse to the 74HC73. I suspect the problem is that your generated clock pulse to the CLK line on the 74HC73 is shorter than the minimum value. Check with a scope. \$\endgroup\$
    – jwh20
    Jan 9, 2021 at 12:22

1 Answer 1

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You need to connect the /R input to Vdd (called Vcc on 74HC chips). Floating, you have a good chance of holding the FF in reset.

All inputs to a 74HCxx chip should be tied to a valid logic level, including the unused flip-flop. Unused outputs can be left open.

You should also have decoupling capacitors across the power supply, preferably one near each chip package. 100nF ceramic is fine.

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