General CMOS circuit

Question

In any CMOS circuit like an inverter or an n-input NOR or NAND gate, where the pMOS network is connected at the top to Vdd source terminal and nMOS network is connected at the bottom to the ground terminal, can any node voltage (junction where two transistors connect) be negative?

In almost all the sources I read it is assumed that the node voltages are always in the range [Vdd, 0]. Of course, this assumption is quite reasonable and intuitive and not worth talking about; but how to 'prove' it logically and through reasoning?

Without this assumption, how to reason/understand, in a CMOS network, which terminal is the source and which terminal is drain for any transistor?

In a network consisting of only capacitors and resistors it is easy to see what the exact voltage of each node is because those devices have simple clearly defined relationship between their voltages and currents/charge across them. How to similarly reason the conclusions about the polarity of each terminal voltage in a transistor network when some transistors are in cutoff and some are conducting?

Answer 1

in any circuit can there be a lower voltage with respect to the negative terminal of the source

Totally different question. The answer to that is obviously "yes"; you know that transformers exist, for example.

In any circuit built from MOSFETS can there be a lower voltage with respect to the negative terminal of the source

Well, I assume that if you understand CMOS, that you also have basics of linear networks.

So you can answer that yourself, negatively, if you model all your transistor source-drain connections as resistive elements.

If you introduce parasitic inductances or capacitances that you use to build inverting power supplies, yes, you can get lower voltages and your original claim breaks down.