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I've a question about the LTSpice simulation of the following simple LC circuit driven by a DC current source.

The first simulation (A) looks good from point of view of initial conditions for either voltage cap V(n001)=0 and inductor current I(L1)=0. As shown in the first picture the Initial Transient Solution (ITS) for the inductor current looks ok.

enter image description here

Consider now the second simulation (B) in which the initial condition has been set just for the inductor current I(L1)=0. This time, as shown in the second picture, that condition seems to be not honored (the initial inductor current results in 10A)

enter image description here

Can you help me in understanding the reason behind it ? Thanks

Edit: based on comments I've done another simulation (C) without any initial condition. As you can see the solver is able to work out the Initial Transient Solution (ITS) different from the previous two (A & B).

enter image description here

Can you point me to some book (or documentation) about how Spice works under the hood ? Thanks

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  • \$\begingroup\$ Both schematic diagrams appear to have the same initial conditions set. You must have changed something so inspect closely what you did. \$\endgroup\$ – Andy aka Jan 9 at 15:40
  • \$\begingroup\$ @Andyaka I suspect the blue one is commented out. \$\endgroup\$ – user_1818839 Jan 9 at 15:41
  • \$\begingroup\$ @BrianDrummond I'm not convinced!! \$\endgroup\$ – Andy aka Jan 9 at 15:41
  • \$\begingroup\$ Be interesting to know the init value of V(n001) that gives the 1GW dissipation though! Presumably, 100MV (at I=10A). Probably due to a simulation limit in source I1. \$\endgroup\$ – user_1818839 Jan 9 at 15:42
  • \$\begingroup\$ I bet LTSpice is trying to solve the initial conditions and, without the active directive, it gets in a mess with a current source and parallel capacitor. \$\endgroup\$ – Andy aka Jan 9 at 15:59
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It does the same in micro-cap. Basically, with any simulator, it tries to ascertain the steady-state initial conditions and, in certain circumstances, it needs to be explicitly told what those initial conditions are. This is one of those circumstances; a current source feeding a capacitor.

The simulator tries to determine the steady state conditions then, once evaluated, it will produce a transient response. But, what are those steady state conditions you might ask. For a simulator, it makes use of the leakage resistance it applies to every circuit node and the default value for micro-cap appears to be 200 MΩ. I get a peak voltage of 2 GV and 2 GV/ 10 amps = 200 MΩ.

In some circumstances (such as these) you need to "force the hand of the simulator" so that the initial conditions are defined as in .ic V(1) = 0.

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  • \$\begingroup\$ not sure to get your point: what is the 'leakage resistance' you are talking about ? In any case, the default value for the initial cap voltage should be zero, don't you ? \$\endgroup\$ – Carlo C Jan 9 at 20:19
  • \$\begingroup\$ Ltspice (as with all other simulators) assumes each node has a tiny leakage to ground. LTSpice (as with all other simulators) tries to stabilise dc conditions before attempting to perform a transient analysis. I’m not asking you to understand this. I’m telling you what happens @Carlo. These things that happen cause the capacitor voltage to be assumed to reach a steady state of millions of volts in the absence of a .ic command that stops the simulator doing this. \$\endgroup\$ – Andy aka Jan 9 at 20:41
  • \$\begingroup\$ An other info: it seems there exist in LTspice a difference when setting initial condition at global level (through .ic directive) with respect to per-instance level. Can you clarify it ? Thanks \$\endgroup\$ – Carlo C Jan 12 at 22:00
  • \$\begingroup\$ I can’t answer that because I don’t use LTSpice. I use micro cap. Maybe ask a new question? \$\endgroup\$ – Andy aka Jan 12 at 23:29
  • \$\begingroup\$ Do you mean another new question ? \$\endgroup\$ – Carlo C Jan 13 at 5:59

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